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Author SHA1 Message Date
Paul Menzel 76d55e5f00 amd/pi/hudson boards: Get rid of power button device 
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD AGESA Hudson boards
(SOUTHBRIDGE_AMD_PI_AVALON).

The GPE ACPI code seems to originate from commit 806def8c (I missed the
svn add on r3787. These are the additional files., Add AMD dbm690t ACPI
support.), and was copied over.

Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2020-06-06 09:44:53 +00:00
Furquan Shaikh b07e262c48 soc/amd/picasso: Add device operations for UART MMIO devices 
This change adds device_operations for UART MMIO devices that provides
following operations:
1. uart_acpi_name: Returns ACPI name of UART device. Generation of
UART device node is not yet moved to SSDT, but will be done in
follow-up CLs.
2. scan_bus: Uses scan_static_bus to scan devices added under the UART
devices. This allows mainboard to add devices under the UART MMIO
device.

Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2020-06-06 09:44:39 +00:00
Mathew King 071182ade3 ec/google/wilco: Always use current value of battery status bit 
According to the Wilco EC spec the BTSC bit of PWSR is always cleared
when PWSR is read so that battery status change events are only
triggered one time. Testing of the Wilco EC has verified this behavior.
This changes the way in which the battery status change bit is used from
checking the bit state against the previous value to always issuing a
battery event when the BTSC bit is set. The other bits in PWSR indicate
state directly and do not behave like the BTSC bit.

BUG=b:157113138
TEST=Deploy on Drallion and verify that battery events are generated
BRANCH=drallion, sarien

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
 2020-06-06 09:43:54 +00:00
Elyes HAOUAS 379aab47f9 src: Remove unused 'include <cpu/x86/mtrr.h>' 
Change-Id: I3f08b9cc34582165785063580b3356135030f63e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
 2020-06-06 09:43:11 +00:00
Elyes HAOUAS cecc4a0d7a cpu/intel/haswell: Remove unused 'include <cpu/x86/bist.h>' 
Change-Id: I5156eb97648927e5fe6e467abb8e3e055a231fec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-06-06 09:43:04 +00:00
Shaunak Saha 48b388f911 mb/intel/tglrvp: Add support for RT 1308 
Add support for RT 1308 audio amplifier in TGLRVP.
We are using the i2c generic driver here to generate
the SSDT file. Datasheet:ALC-1308-CG-version-08.

BUG=none
BRANCH=none
TEST=Build and boot tglrvp successfully. In kernel console
use the "aplay -l" command to check soundcard is listed.

Change-Id: I41d205a3ab87db85baf49e9e8a582c226ba5832d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
 2020-06-06 09:42:25 +00:00
Tony Huang 8679ad6eb6 mb/google/octopus/variants/garg: Add G2Touch touchscreen support 
BUG=b:156564296
BRANCH=octopus
TEST=emerge-octopus coreboot

Change-Id: I99b04fec88da481e21b7a05807a4f1edeb3a5bdf
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
 2020-06-06 09:42:14 +00:00
Raul E Rangel be2b5ac0ea soc/amd/picasso: Use MSR_CSTATE_ADDRESS 
This is a standard MSR. No reason for picasso to define its own.

BUG=b:147042464
TEST=Boot to OS on trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:41:44 +00:00
Raul E Rangel f9b9166431 soc/amd/picasso: Remove call to setup_bsp_ramtop 
We don't use amd_setup_mtrrs, bsp_topmem or bsp_topmem2 in picasso.

BUG=b:147042464
TEST=Boot to OS on trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1941934975dfea4f189347811b003a33996c887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-06-06 09:41:28 +00:00
Elyes HAOUAS abf51abe1d src: Remove unused '#include <cpu/x86/smm.h>' 
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:40:38 +00:00
Kyösti Mälkki e1df7eef91 drivers/pc80/rtc: Drop ARCH_X86 guard in header 
Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:40:17 +00:00
Edward O'Callaghan 7c52283f78 chromeos/cr50_enable_update.c: Modify recovery flow for cr50 
Enable Cr50 update in recovery mode, so that we can at least still
update the process for most cases (that an update is pending in recovery
mode is not impossible but should be unlikely in the field).

Leave manual recovery unaffected so at least that would still work even
if Cr50 wedges in a weird way that it thinks it has an update on every
boot or something.

Setting the recovery_reason to VB2_RECOVERY_TRAIN_AND_REBOOT allows the
update to be applied.

BUG=b:154071064
BRANCH=none
TEST=builds

Thanks to Julius Werner for the suggested fix.

Change-Id: Iba341a750cce8334da4dcf6353ca8cd1268d170f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2020-06-06 09:39:07 +00:00
Jamie Ryu 5131c6f79a soc/intel/tigerlake: Add CPU ID for TGL B0 
Reference:
- TGL User Guide #613584 Rev 2.2
- TGL User Guide #605534 Rev 1.0

BRANCH=none
BUG=none
TEST=build and boot tglrvp

Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41516
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:38:34 +00:00
Elyes HAOUAS 04506e2987 sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register 
Change-Id: I779387fb0c9d3ad6e16d4ccfc39c38dfe6620345
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-06-06 09:36:10 +00:00
Furquan Shaikh efea70c0ee mb/google/dedede/var/wheelie: Add memory parts and generate DRAM IDs 
This change adds memory parts used by variant wheelie to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.

BUG=b:157862308

Change-Id: I53f6f5c832cd40068a6d4379ace849f6e8ad7a91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41990
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:31:31 +00:00
Furquan Shaikh aec0e31028 mb/google/dedede: Drop .spd.hex files from spd/ 
Now that dedede is moved to using the auto-generated SPDs, we no
longer need the .spd.hex files in spd/ folder. Hence, this change
drops the files.

Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41882
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:31:22 +00:00
Furquan Shaikh 4612632edc mb/google/dedede: Switch to using auto-generated SPDs 
This change switches dedede and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.

Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:31:12 +00:00
Furquan Shaikh b9adb11edf mb/google/dedede: Drop selection of GENERIC_SPD_BIN 
GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and
have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it
already provides its own rules for SPD inclusion. In follow up
changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool
to use similar suffixes and allowing different paths to be provided
for SPD by mainboard.

Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:30:48 +00:00
Furquan Shaikh 038757d2d0 mb/google/dedede/var/waddledoo: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by waddledoo and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte#    Current     New         Explanation
4        0x15        0x16        This part has only 1 die. Hence,
                                 density per die is 16Gb.
6        0x90        0x04        1 die in package and 2 channels per
                                 die.
9        0x40        0x00        Unused by MRC.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xFF as
                                 per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.

Part: NT6AP256T32AV-J2
Waddledoo started assigning DRAM part IDs from 1. So, this change
fills in Nanya part as ID 0 (though it is currently unused).

Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-06-06 09:30:34 +00:00
Furquan Shaikh a39d54edce mb/google/dedede/var/wheelie: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by wheelie and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte#    Current     New         Explanation
4        0x15        0x16        This part has only 1 die. Hence,
                                 density per die is 16Gb.
6        0x90        0x04        1 die in package and 2 channels per
                                 die.
9        0x40        0x00        Unused by MRC.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xFF as
                                 per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.

Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-06-06 09:30:22 +00:00
Furquan Shaikh f3a642de6d mb/google/dedede/var/waddledee: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by waddledee and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte#    Current     New         Explanation
4        0x15        0x16        This part has only 1 die. Hence,
                                 density per die is 16Gb.
6        0x90        0x04        1 die in package and 2 channels per
                                 die.
9        0x40        0x00        Unused by MRC.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xFF as
                                 per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.

Part: NT6AP256T32AV-J2
Byte#    Current     New         Explanation
4        0x14        0x15        This part has only 1 die. Hence,
                                 density per die is 8Gb.
6        0x90        0x04        1 die in package and 2 channels per
                                 die.
Manufacturer name bytes are set to 0.

Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-06-06 09:30:12 +00:00
Furquan Shaikh 20ecf2268b lp4x: Add new memory parts and generate SPDs 
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR

BUG=b:157862308, b:157732528

Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:29:54 +00:00
Furquan Shaikh 4a93ba9f77 mb/google/volteer: Drop spd/ folders from variants/ 
Now that volteer is moved to using the auto-generated SPDs, we no
longer need the spd/ folder under each variant. Hence, this change
drops the spd/ folders and the SPD files within them.

BUG=b:156126658

Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41619
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:29:38 +00:00
Furquan Shaikh 9ddc2c54fc mb/google/volteer: Switch to using auto-generated SPDs 
This change switches volteer and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.

BUG=b:147321551,b:155423877

Change-Id: I9ed48f0b51714b072a0459d0b70b5417a49db54f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-06-06 09:29:29 +00:00
Furquan Shaikh 2ccb972df4 mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by volteer and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: K4U6E3S4AA-MGCL
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

Part: K4UBE3D4AA-MGCL
Byte#    Current     New         Explanation
6        0xB5        0xB4        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.

Part: H9HCNNNBKMMLXR-NEE
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. tckMin is
                                 calculated as (1/4267)*2 which comes
                                 out to be 0.46871. Some datasheets
                                 round this down to 0.468 and others
                                 round it up to 0.469. JEDEC spec uses
                                 0.468. As per that, this value comes
                                 out to be 0xE0.

Part: H9HCNNNFAMMLXR-NEE
Byte#    Current     New         Explanation
4        0x15        0x16        As per datasheet, density is 16Gb per
                                 logical channel. So value should be 0x16.
6        0xF9        0xB8        This device has 4 logical dies
                                 instead of 8. Also, signal loading is
                                 not used by MRC.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
20,21,   0x92,0x55,  0x12,0x29,  As per datasheet, part supports CAS
22       0x00        0x15        latencies 6,10,16,22,26,32,36,40. So value
                                 should be 0x12,0x29,0x15.
24       0x8C        0x96        taa is .468ns * CAS-40 which results
                                 in byte 24 being 0x96 as per datasheet.
29,30    0xE0,0x0B   0xC0,0x08   As per datasheet, this corresponds to
                                 280ns in MTB units which is 0x08C0.
31,32    0xF0,0x05   0x60,0x04   As per datasheet, this corresponds to
                                 140ns in MTB units which is 0x04C0.
123      0x00        0xE2        Fine offset for taa. Expected value
                                 is 0xE2 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. tckMin is
                                 calculated as (1/4267)*2 which comes
                                 out to be 0.46871. Some datasheets
                                 round this down to 0.468 and others
                                 round it up to 0.469. JEDEC spec uses
                                 0.468. As per that, this value comes
                                 out to be 0xE0.

Part: MT53E1G32D2NP-046 WT:A
Byte#    Current     New         Explanation
4        0x15        0x16        As per datasheet, density is 16Gb per
                                 logical channel. So value should be 0x16.
5        0x21        0x29        As per datasheet, this part has 17row
                                 address bits and 10column address
                                 bits. This results in 0x29.
6        0xB5        0x94        This device has 2 logical dies. Also,
                                 MRC does not use signal loading.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
12       0x0A        0x02        As per datasheet, this is 1rank and
                                 16-bit wide channel. So, value should
                                 be 0x02.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
29,30    0xC0,0x08   0xE0,0x0B   As per datasheet, this corresponds to
                                 380ns in MTB units which is 0x0BE0.
31,32    0x60,0x04   0xF0,0x05   As per datasheet, this corresponds to
                                 190ns in MTB units which is 0x05F0.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.
BUG=b:147321551,b:155423877

Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-06-06 09:29:16 +00:00
Furquan Shaikh 7d6697d51c mb/google/volteer/var/halvor: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by halvor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: H9HKNNNCRMBVAR-NEH
Byte#    Current     New         Explanation
4        0x16        0x15        As per datasheet, density is 8Gb per
                                 logical channel. So value should be 0x15.
6        0xB9        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00. 2 channels 2
				 dies. Hence, 0x94
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
29,30    0xE0,0x0B   0xC0,0x08   As per datasheet, this corresponds to
                                 280ns in MTB units which is 0x08C0.
31,32    0xF0,0x05   0x60,0x04   As per datasheet, this corresponds to
                                 140ns in MTB units which is 0x0460.
125      0xE1        0xE0        Fine offset for tckMin. tckMin is
                                 calculated as (1/4267)*2 which comes
                                 out to be 0.46871. Some datasheets
                                 round this down to 0.468 and others
                                 round it up to 0.469. JEDEC spec uses
                                 0.468. As per that, this value comes
                                 out to be 0xE0.

Part: MT53E1G64D4SQ-046 WT:A
Byte#    Current     New         Explanation
5        0x21        0x29        As per datasheet, this part has 17row
                                 address bits and 10column address
                                 bits. This results in 0x29.
6        0xB9        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00. 2 channels,
				 2 dies. Hence, 0x94.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

BUG=b:147321551,b:155423877

Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:29:06 +00:00
Furquan Shaikh 459655abe7 mb/google/volteer/var/malefor: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by malefor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: K4U6E3S4AA-MGCL
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Bits 1:0 set to 0.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

BUG=b:155239397,b:147321551

Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:28:56 +00:00
Furquan Shaikh ae7ebcb316 mb/google/volteer/var/ripto: Use auto-generated Makefile.inc using gen_part_id.go 
This change adds mem_list_variant.txt that contains the list of
memory parts used by ripto and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: K4U6E3S4AA-MGCL
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Bits 1:0 set to 0.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

BUG=b:155239397,b:147321551

Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:28:46 +00:00
Furquan Shaikh 17dfa7e25c soc/intel/jasperlake: Generate LP4x SPD files using gen_spd.go 
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that
can be used with JSL-based mainboards.

Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go

Mainboards can use the SPD files from SoC directly when creating
SPD binary to add to CBFS.

Change-Id: Ic52506b809c66b9f7cf25a100a959d85c67addf2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41876
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:28:31 +00:00
Furquan Shaikh 5ce3bca1e7 soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.go 
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with TGL-based mainboards.

Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go

Mainboards can use the SPD files from SoC directly when creating SPD
binary to add to CBFS.

BUG=b:147321551,b:155239397

Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-06-06 09:28:17 +00:00
Furquan Shaikh 4bd95295f1 util/spd_tools/intel/lp4x: Add a global list of LP4x memory parts 
This change adds a JSON file (`global_lp4x_mem_parts.json.txt`)
containing global list of LP4x memory parts to live along with the spd
tools since the part information is not really any SoC or mainboard
dependent and comes directly from the part datasheet. It can be shared
by mainboards based on different platforms supported by the tools.

BUG=b:155239397,b:147321551

Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:27:59 +00:00
Furquan Shaikh 70001fe1f7 util: Add spd_tools to generate SPDs for TGL and JSL boards 
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.

In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for LPDDR4x
memory used in memory down configurations on Intel Tiger Lake (TGL)
and Jasper Lake (JSL) based platforms. These tools generate SPDs
following JESD209-4C specification and Intel recommendations (doc

Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
  part list provided by the mainboard in JSON format. Additionally,
  generates a SPD manifest file (in CSV format) with information about
  what memory part from the global list uses which of the generated
  SPD files.

* gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x
  memory parts used by the board. Takes as input list of memory parts
  used by the board (with one memory part on each line) and the SPD
  manifest file generated by gen_spd.go. Generates Makefile.inc for
  integrating the generated SPD files in the coreboot build.

BUG=b:155239397,b:147321551

Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-06-06 09:27:44 +00:00
Elyes HAOUAS ae96874e48 mb/google/dedede/board_info.c: Clean up 
Remove unused includes

Change-Id: I7e8109870168db7f477f205a0b3020b7b2be5f5f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41541
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:26:45 +00:00
Caveh Jalali 96f231ac4b usb/xhci: Fix timeout logic 
This fixes a logic bug in how timeouts are reported back. In the
timeout case, the original code would return -1 instead of 0. All call
sites expect a return value of 0 as the timeout indicator.

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-06-06 09:26:02 +00:00
Kyösti Mälkki 0a9e72e87e arch/x86: Declare permanent_smi_handler() 
Advertising SMI triggers in FADT is only valid if we exit with
SMI installed. There has been some experiments to delay SMM
installation to OS, yet there are new platforms that allow some
configuration access only to be done inside SMM.

Splitting static HAVE_SMI_HANDLER variable helps to manage cases
where SMM might be both installed and cleared prior to entering
payload.

Change-Id: Iad92c4a180524e15199633693446a087787ad3a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-06-06 09:24:44 +00:00
Kyösti Mälkki c328a680de soc,southbridge/intel: Control SMI related FADT entries 
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.

Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:24:11 +00:00
Kyösti Mälkki 2e270ae297 mb/emulation/qemu-q35: Control SMI related FADT entries 
If running on older (like before 2.4.0) version of QEMU there is
no SMI support, so never advertise SMI in FADT for the emulation.
Behaviour if ACPI daemon tries to raise SMI under these conditions
is unknown.

Change-Id: I170058793798648c6713de1530d89ec2ac53e39a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-06-06 09:23:45 +00:00
Kyösti Mälkki 9145ce2149 mb/lenovo/t400,x200: Control SMI related FADT entries 
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.

Change-Id: Ia61e50fb49719e9e18e81a27f355cdbd755a3f40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:23:20 +00:00
Kyösti Mälkki c6f2e58a64 mb/roda/rk9: Control SMI related FADT entries 
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.

Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-06 09:22:55 +00:00
Christian Walter b646e28769 mb/prodrive/hermes: Add new mainboard port 
This patch adds support for the Prodrive Hermes mainboard.

Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41.

Untested:
* CNVi
* Intel Graphics

Tested:
* CPU Intel Xeon E2288G
* CPU Intel Core i3-9100F
* CPU Intel Core i7 9700KF
* CPU Intel Core i7 9700E
* CPU Intel Core i7 9700F
* CPU Intel Core i5 9600K
* CPU Intel Pentium Gold G5400
* PCIe Link Width x8 on Slot6 by changing PCIe mux
* All four DDR4 slots in different configurations
* USB2.0 HDR1
* USB2.0 HDR2
* USB3.0 HDR
* Slot1
* Slot2
* Slot3
* Slot4
* Slot6
* M2.M NVMEe
* Ethernet PHYs 0-4
* Aspeed BMC PCIe
* Aspeed BMC USB
* Aspeed Graphics init
* USB3 backplane all working
* I801 SMBUS

Not Working:
* Intel HDA

Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2020-06-06 07:44:53 +00:00
Jonathan Zhang b7cf7d36d7 soc/intel/xeon_sp/cpx: set up cpus 
Set up cpus:
* setup apic IDs.
* setup MSR to enable fast string, speed step, etc.
* Enable turbo

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I5765e98151f6ceebaabccc06db63d5911caf7ce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 2020-06-06 07:44:07 +00:00
Caveh Jalali eaa219b5bb libpayload: drivers/usb: add a USB pre-poll hook 
This adds a hook so that a payload can optionally perform USB service
functions in conjunction with regular USB port status polling. In
particular, this allows depthcharge to control the state of an
external USB mux. Some SoCs like Tiger Lake have a USB mux for Type-C
ports that must be kept in sync with the state of the port as reported
by the TCPC. This can be achieved by hooking into the poll routine to
refresh the state of the USB mux.

BUG=b:149883933
TEST=booted into recovery from Type-C flash drive on volteer

Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2020-06-06 01:49:52 +00:00
Tim Wawrzynczak a4e2e0550c Documentation: Add section about 'hidden' devices to 4.13 release notes 
CB:41384 (SHA dbcf7b1621) added some new
functionality to devicetree files ("hidden PCI devices"). It's a decent
enough semantic change that it should be added to the release notes for
the 4.13 release.

Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-06-06 01:33:38 +00:00
Julius Werner 554b03038e google/trogdor: Remove RO_FSG region 
We decided to store the FSG on eMMC instead of SPI flash, so we don't
need this region anymore. Getting rid of it allows us to put more space
into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining
amount to keep the FMAP alignment reasonable.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
 2020-06-05 21:42:26 +00:00
Felix Held 017ec16588 soc/amd/common/spi: add and use define for last FIFO position 
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but
turned out to be correct.

Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-05 19:51:47 +00:00
Furquan Shaikh 466374924c soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devices 
This change adds a helper function set_mmio_dev_ops() in chip.c which
is used for setting the dev->ops for MMIO devices based on the
comparison of MMIO address in device tree to the pre-defined base
addresses in iomap.h.

Call to i2c_acpi_name() is replaced with set_mmio_dev_ops and scope of
i2c_acpi_name is restricted to i2c.c since it is not required to be
exposed out of that file.

Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2020-06-05 14:08:06 +00:00
Angel Pons 1929b571ce sb/intel/bd82x6x: Remove dead code 
Drop functions that are not being used.

Change-Id: If406601f3bb7a98a621c1339b2f3413a43b8cc9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-06-05 12:52:50 +00:00
Raul E Rangel 24ee0b5991 Revert "mb/google/zork: Increase RO section to 5MB" 
This reverts commit fddd101904188193197be10c8eae04e76386299b.

Reason for revert: With FSP compression and non serial FSP we now have enough space in RO.

Original change's description:
> mb/google/zork: Increase RO section to 5MB
>
> The current size is too small to fit all the depthcharge assets.
> Increasing it to 5MB gives us 648k of free space.
>
> $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT
> FMAP REGION: COREBOOT
> Name                           Offset     Type           Size   Comp
> cbfs master header             0x0        cbfs header        32 none
> fallback/romstage              0x80       stage          524316 none
> fallback/ramstage              0x80100    stage           96592 none
> config                         0x97ac0    raw               843 none
> revision                       0x97e80    raw               680 none
> spd.bin                        0x98180    spd              8192 none
> etc/sdcard0                    0x9a1c0    raw                 8 none
> locales                        0x9a200    raw               141 LZMA (166 decompressed)
> (empty)                        0x9a300    null             3224 none
> fspm.bin                       0x9afc0    fsp            720896 none
> (empty)                        0x14b000   null             3992 none
> fsps.bin                       0x14bfc0   fsp            327680 none
> pci1002,15d8,c1.rom            0x19c000   optionrom       54272 none
> pci1002,15d8,c4.rom            0x1a9480   optionrom       54272 none
> fallback/dsdt.aml              0x1b6900   raw             12727 none
> locale_hi.bin                  0x1b9b00   raw             10441 LZMA (239928 decompressed)
> ...
> locale_ko.bin                  0x254f80   raw             11282 LZMA (231168 decompressed)
> fallback/payload               0x257c00   simple elf      95169 none
> (empty)                        0x26f000   null           245656 none
> apu/amdfw                      0x2aafc0   raw           1277440 none
> (empty)                        0x3e2e00   null           688472 none
> bootblock                      0x48af80   bootblock          64 none
>
> BUG=b:130028876
> BRANCH=none
> TEST=Built image with depthcharge and booted.
>
> Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2042850
> Reviewed-by: Martin Roth <martinroth@google.com>

BUG=b:130028876, b:150746858
BRANCH=none
TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle
localhost ~ # flashrom -p host -r /tmp/main.bin
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
Calibrating delay loop... OK.
coreboot table found at 0xcbe54000.
Reading flash... SUCCESS

localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3
area:            22
area_offset:     0x00c00000
area_size:       0x00400000 (4194304)
area_name:       WP_RO

localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
SUCCESS

localhost ~ # flashrom -p host --wp-status
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9  : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
WP: status: 0x0094
WP: status.srp0: 1
WP: status.srp1: 0
WP: write protect is enabled.
WP: write protect range: start=0x00c00000, len=0x00400000

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-06-04 23:06:41 +00:00
Duncan Laurie e530d816cc drivers/uart/acpi: Add new device driver for UART attached devices 
This driver generates an ACPI device object for a UART attached device
with all of the expected device support handlers like different interrupt
sources and power control GPIOs.

Example use:
chip drivers/uart/acpi
    register "name" = ""UDEV""
    register "desc" = ""UART Attached Device""
    register "hid" = "ACPI_DT_NAMESPACE_HID"
    register "compat_string" = ""google,cros-ec-uart""
    register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)"
    register "uart" = "ACPI_UART_RAW_DEVICE(115200, 64)"
    device generic 0 on end
end

Resulting in this ACPI device:

Device (UDEV)
{
    Name (_HID, "PRP0001")
    Name (_UID, Zero)
    Name (_DDN, "UART Attached Device")
    Method (_STA, 0, NotSerialized)
    {
        Return (0x0F)
    }
    Name (_CRS, ResourceTemplate ()
    {
        UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne,
                         0x00, LittleEndian, ParityTypeNone, FlowControlNone,
                         0x0040, 0x0040, "\\_SB.PCI0.UAR2",
                         0x00, ResourceConsumer, , Exclusive)
        GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000,
                 "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer)
        {
            0x0114
        }
    })
    Name (_DSD, Package (0x02)
    {
        ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
        Package (0x01)
        {
            Package (0x02)
            {
                "compatible",
                "google,cros-ec-uart"
            }
        }
    })
}

Change-Id: Idfd2d9d2ab6990a82ddd401734c0d9b1b0b8f82d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-06-04 20:08:32 +00:00
Duncan Laurie dccef0da0c acpi: Add support for writing UART device descriptors 
This change adds support for generating the device descriptor that
corresponds to the UARTSerialBusV2() ACPI macro.

The resulting ACPI code for ACPI_UART_RAW_DEVICE(115200, 64) is:

UartSerialBusV2 (0x0001C200, DataBitsEight, StopBitsOne,
                 0x00, LittleEndian, ParityTypeNone, FlowControlNone,
                 0x0040, 0x0040, "\\_SB.PCI0.UAR2",
                 0x00, ResourceConsumer, , Exclusive)

Change-Id: I671ce2a499d74717d8677528c46ab3fbc1d7faf5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-06-04 20:08:09 +00:00