Commit Graph

2444 Commits

Author SHA1 Message Date
Marc Jones ba8965c039 Changed the stop_this_cpu() to just hlt.
Removed local APIC INIT (don't worry the APIC and AP are still initialized).

The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
The Intel Multiprocessor specification indicated that a vector should be set
and a START should happen following an INIT. Then AP will execute the 
instructions pointed to by the vector. There is no vector or start in
stop_this_cpu(). This seems to put the AP in an in-between state. In the case
of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
debugger.

The better solution seems to be to just put the AP in a hlt and allow the AP
to go into C1. Then APIC managing software running on the BSP can program the
AP as needed.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:52:11 +00:00
Marc Jones 2ce8bfd251 Initial AMD Serengeti_Cheetah_FAM10 platform for Barcelona support.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:49:44 +00:00
Marc Jones 0da5cdeac2 Additional early AMD8111 southbridge support for Barcelona platforms.
Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.


Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:36:46 +00:00
Marc Jones 8ae8c88220 Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:32:08 +00:00
Marc Jones 2006b38fed Whitespace and other code cleanup in peperation for AMD Barcelona support.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 00:47:09 +00:00
Carl-Daniel Hailfinger 244dd82fd6 Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,
M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets and double checked.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 22:22:40 +00:00
Ulf Jordan e9690bddd5 Add dump support for NSC PC87317.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 22:10:00 +00:00
Uwe Hermann 8ef47da471 Enable IDE legacy port access for all 440BX based boards per default, as
this is needed (at the very least) to make FILO work on these boards.

Disable UDMA/33 per default, which is slower but the safe choice, as we
don't know which IDE devices a user has attached, and some don't support
UDMA/33 very well or at all.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 21:34:53 +00:00
Carl-Daniel Hailfinger 12a3f1edec To make it easier to add new SPI chips to flashchips.c, rename functions
with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 14:33:32 +00:00
Carl-Daniel Hailfinger 3b408fd237 Add support for ST M25P80 chips to flashrom. Detection was tested.
Print status register before erase to help debugging block locks.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-16 21:15:27 +00:00
Ulf Jordan c9a677b4b3 Add dump support for SMSC LPC47M192.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-14 20:00:58 +00:00
Ulf Jordan c7e12e2a9d Add dump support for NSC PC97317.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-14 00:04:16 +00:00
Ulf Jordan aa6dd7407d Add detection and dump support for NSC PC97307.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-13 23:56:16 +00:00
Ulf Jordan 48c7032c28 Add dump support for NSC PC8741x.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-13 23:41:45 +00:00
Frederico Silva 850c01cacf Add support for more atmel chips:
AT49F002
AT49F002N
AT49F002T
AT49F002NT

Only tested the read function on AT49F002T.
datasheet @ http://www.atmel.com/atmel/acrobat/doc1017.pdf

Signed-off-by: Frederico Silva <frederico.silva@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-10 16:57:59 +00:00
Myles Watson 15674b78be This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to every
Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA"
line in it.

I figure that only adding it to the files that already have support
for LZMA payloads makes sure I don't break anything.

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-09 17:18:29 +00:00
Ulf Jordan 94a84dee9e Add detection and dump support for NSC PC87309.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-08 00:17:19 +00:00
Uwe Hermann 11887f258d Add/fix some LDN descriptions (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-07 23:55:20 +00:00
Ulf Jordan 25df0c586a Fix typo. According to National's datasheet PC87317 has SID = 0xd0 and
PC97317 has SID = 0xdf. PC87371/PC97371 do not seem to exist.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-07 21:55:12 +00:00
Uwe Hermann 435325e7ac Remove the coherent_ht_car.c file. It is exactly the same as
coherent_ht.c (save one empty line removed) so there's no use
to keep it around.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-05 19:26:55 +00:00
Uwe Hermann 186a3875dc Various coding style fixes, constification, fixed typos (trivial).
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-04 21:49:06 +00:00
Ward Vandewege 17e993214f Enable vga option rom support for 1MB rom chip, which is what the h8dmr ships with (trivial).
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-04 01:15:29 +00:00
Jonathan A. Kollasch d795b9a9ec Add board-enable for Acorp 6A815EPD.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-02 19:03:23 +00:00
Uwe Hermann 9da69f83d9 Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):
- Implement ISA related support:
   - Initialize the RTC
   - Enable access to all BIOS regions (but _not_ write access to ROM)
   - Enable ISA (not EIO) support
   - Without the *_isa.c file, the Super I/O init is never performed
 - Improve IDE support:
   - Add config option to enable Ultra DMA/33 for each disk
   - Add config option to enable legacy IDE port access
 - Implement hard reset support
 - Implement USB controller support
 - Various code cleanups and improvements

The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-30 02:08:26 +00:00
Stefan Reinauer 8d43b343cf fix abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 15:01:53 +00:00
Uwe Hermann 59b99d9071 Various small fixes (trivial).
- Add missing contributors to the README.

 - Drop obsolete -D option from manpage.

 - Only list contributors who added non-trivial amounts of code as copyright
   holders (and do not list those who merely provided register dump support
   for Super I/Os). Those contributors are still listed in the README,
   of course. See discussion in the thread starting at
   http://www.linuxbios.org/pipermail/linuxbios/2007-October/025516.html

 - Make a function static.

 - Fix incorrect URL in code comment. Drop obsolete comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 02:43:50 +00:00
Mondrian Nuessle 8e290d38e4 Flashrom does not work after booting LinuxBIOS on the Iwill DK8-HTX board,
according to mcqmcqmcq@fastmail.fm. Fix it.

Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
Acked-by: mcq <mcqmcqmcq@fastmail.fm>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 02:28:55 +00:00
Uwe Hermann 447aafe5db Restructure/rename/comment a few 82371XX-related PCI IDs (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 01:44:43 +00:00
Uwe Hermann 8708c1b7c3 Update AMD CPU IDs in model_fxx_init.c with information from
the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for
AMD Athlon 64 and AMD Opteron Processors' datasheet.

Also, add information about the CPU socket for each ID (as per datasheet).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 01:25:29 +00:00
Uwe Hermann 020724fc70 Drop the unfinished, non-working Bitworks IMS board.
It never worked in v2 (the v1 port did work AFAIK, though), and it's
not really useful as reference for other boards anymore (as we now
have a dozen or so 440BX boards which work in v2).

This is a specialized, custom board (not sold on the "public market"),
so it's probably not useful for pretty much everyone out there anyway.

We can easily re-add it later (based on one of the other 440BX boards)
should there be interest and/or someone with the hardware to test.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-27 01:24:46 +00:00
Ronald G. Minnich 254f47ef98 Correction to irq tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-26 21:43:21 +00:00
Robinson P. Tryon 29cbb367b0 Dump support for SMSC FDC37C67x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 21:43:29 +00:00
Corey Osgood d1bfaa92e8 More abuild fixes, the previous ones weren't enough. Hopefully this covers everything.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 03:49:43 +00:00
Corey Osgood c29533a37d Small abuild fix for the iwill dk8_htx and latest iasl. Building this still fails for me, but it's an lzma error and probably Debian's fault.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 01:08:20 +00:00
Corey Osgood 44a115706b abuild fix for the asus a8v-e_se and newest iasl version (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 00:58:09 +00:00
Corey Osgood 4617191ca1 abuild fix for the amd serengeti_cheetah and the latest iasl version (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 00:50:06 +00:00
Uwe Hermann 13f7a00200 Fix abuild for ASUS MEW-AM.
You cannot set 'default ROM_SIZE = 0' in Options.lb (and override it in
targets/*/Config.lb). While it'll work for manual builds, abuild doesn't
cope with that very well. So set a valid value in Options.lb, too.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 00:13:51 +00:00
Uwe Hermann cc454483b4 Add support for the ASUS MEW-AM board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-24 22:09:38 +00:00
Ulf Jordan 4dea67193e Add dump support for the PC87366.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-24 21:49:39 +00:00
Uwe Hermann 33715eb95c Mark devices which are not available on the board with "N/A" to
make it clearer why they are disabled (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-22 14:55:13 +00:00
Uwe Hermann f811edefd9 Dump support for the SMSC LPC47B27x (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-22 03:36:18 +00:00
Morgan Tsai c8cf4ad422 1. Fix pirq routing table setting for GA-2761GXDK.
2. Southbridge PCIe slots are working correctly now.
3. Disable keyboard & mouse ports for GA-2761GXDK.

Signed-off-by: Morgan Tsai <my_tsai@sis.com> 
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-20 14:11:24 +00:00
Uwe Hermann 74b29b9e33 Detection support for more Super I/Os. Small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-17 17:13:52 +00:00
Uwe Hermann 70ab323ae6 Various cosmetic fixes and improvements (trivial).
- Use 'static' where appropriate.
 - Use 'const' where appropriate.
 - Indentation fixes.
 - Add comment wrt init code which is only valid for VT8237R.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-15 15:52:42 +00:00
Carl-Daniel Hailfinger e13abe53b4 Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal.
Reason: The existing code does not tell us why it sets the watchdog
clock at all, but since it appears in cache_as_ram_auto.c instead of
the usual place (Config.lb) there has to be some meaning to it.
Simply do what the proprietary bios does: Use the external clock source.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 17:57:04 +00:00
Carl-Daniel Hailfinger 34153ac0b8 Autodetect presence of serial flash and set up the board accordingly.
This enables us to have only one configuration and one set of code for
all revisions of the Gigabyte GA-M57SLI-S4.
Flash is now setup correctly for both SPI and LPC flash.

Detection of SPI flash in flashrom on rev. 2.x boards now hangs
instead of failing. However, that is just an effect of the combination
of incomplete initialization of the SPI controller and paranoid checks
in the flashrom SPI code.
If anyone wants to work on that, he needs a logic analyzer or creative
imagination. Hint: LPC-to-SPI read passthrough, clock signal.

Remaining issues for the M57SLI: Fan/environment control.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 15:09:30 +00:00
Morgan Tsai 31e805dadb * Maintaining SiS south bridge device IDs.
* Strip unnecessary driver modules.

Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 01:34:02 +00:00
Uwe Hermann 4c28034e58 Add detection and dump support for the SMSC FDC37N958FR (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 00:30:36 +00:00
Uwe Hermann 5fd9a78a9d Small fix to make abuild happy (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 23:32:03 +00:00
Stefan Reinauer 59ef59ea94 Fix ACPI issues brought up with Intel's latest ASL compiler.
iasl now defaults to put created files into the input file's path, not into the
current directory.

This (trivial) patch fixes the behavior for the northbridge specific ASL code.

Further checkins to be expected.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 21:20:13 +00:00