Commit Graph

29230 Commits

Author SHA1 Message Date
Arthur Heymans 8a2056cac4 mainboard/intel/saddlebrook: Remove unused functions
Setting up the SIO serial console is done in the bootblock.

Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32985
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 21:21:31 +00:00
John Zhao 317cbd6f02 src/soc/intel: Avoid NULL pointer dereference
Coverity detects pointer mem_info as NULL_RETURNS. Add sanity check
for mem_info to prevent NULL pointer dereference.

BUG=CID 1401394
TEST=Built and boot up to kernel.

Change-Id: I9d78ab38b8b2dd3734e0143acfd88d9093f16ce6
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33152
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 18:24:06 +00:00
Nico Huber 9995418166 soc/intel: Replace UART_BASE() and friends with a Kconfig
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.

As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.

Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 15:23:49 +00:00
Arthur Heymans 10ed374d7d sb/intel/i82801ix: Select SOUTHBRIDGE_INTEL_COMMON_SPI
This allows to use the CONFIG_CONSOLE_SPI_FLASH.

Change-Id: I563c69ce6337d46380f889f42633e858ac207916
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 15:02:32 +00:00
Christian Walter 4b55935173 src/soc/intel/common/block/sgx: Add missing new lines
Added missing new lines to Debug Output.

Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:35:39 +00:00
Marshall Dawson 920bab553e soc/amd/stoneyridge: Fix alignment in iomap.h
Change-Id: I79e8bc425d5db45abaeb655f86773f3bb1b2f8c4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-03 13:35:30 +00:00
Elyes HAOUAS c6d503fb81 sb//nvidia/mcp55/mcp55.c: Remove variable set but not used
Change-Id: I40cae58a7a7c9c3c20367541853001510a59e42b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33061
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:34:02 +00:00
Elyes HAOUAS 6b7171b32c nb/amd/pi/00630F01/northbridge.c: Remove variable set but not used
Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-03 13:32:50 +00:00
Elyes HAOUAS 95794693cb sb/nvidia/ck804: Remove variable set but not used
Change-Id: Ia8586e229e04fa11696a846653a3a54909ca7c1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-03 13:32:31 +00:00
Elyes HAOUAS 99f1d50335 cpu/amd/family_10h-family_15h: Remove variable set but not used
Change-Id: Ifc63ec5b588f8edcec5eda343ec9694332845045
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33006
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:32:19 +00:00
Elyes HAOUAS 4be1f8a2f6 sb/nvidia/mcp55: Remove variable set but not used
Change-Id: Ic8f6c264aedbdab0eacb6a99a32cc90336e08d84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33011
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:30:12 +00:00
Elyes HAOUAS 156936b771 nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not used
Change-Id: Icd9c0541d9006f4ebddcefff9d2355056af0c5c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32972
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:29:59 +00:00
Elyes HAOUAS 1a7623bc1a drivers/aspeed/ast2050: Remove variable set but not used
Change-Id: Iedda92edf8c4eb7be037dcc0faa6fe8aa0c0754c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-03 13:29:26 +00:00
Elyes HAOUAS 19cb6c9980 sb/intel/fsp_rangeley: Remove variable set but not used
Change-Id: Ia2bc9bb0f0ece5ae3a57662b54f3e7e78ce00b19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-03 13:29:08 +00:00
Elyes HAOUAS 9c8895fd88 nb/intel/sandybridge: Remove variable set but not used
Change-Id: I75f5d821e018932d3f10d84b7ebed362777fb17d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32938
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:28:34 +00:00
Elyes HAOUAS fa1f7216ce nb/intel/sandybridge: Remove variable set but not used
Change-Id: Iaac05f73d2ba892d3ec7ee2ac0c16a98f2fce5bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32926
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:28:03 +00:00
Nico Huber 10ed868d19 soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode()
This is never called: The only calling path is guarded by both
!DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the
latter selects the former.

If somebody figures out how this is supposed to be used, we can
easily revive the implementation.

Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:26:00 +00:00
John Zhao 2deb5fb3b0 src/device: Prevent attack on null pointer dereference
Clang Static Analyzer version 8.0.0 detects access to field dev results
in a dereference of a null pointer which is loaded from variable bus.
Add sanity check for pointer bus to prevent null pointer dereference.

TEST=Built and boot up to kernel.

Change-Id: I084906c33065eaa834f50c545efcfab620658ec9
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-06-03 13:25:25 +00:00
Nico Huber 62ddc491cf soc/intel/common/uart: Correctly guard uart_platform_base()
We should only provide this implementation when the Intel LPSS UART is
used. Otherwise, no other UART could be used for the console with these
SoCs.

Change-Id: Iebd89edb3f21d4a68587fd02659b4d529f3f4bbe
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-03 13:24:27 +00:00
Nico Huber ce8eebd3b7 soc/intel/common/uart: Only return valid UART base
We only configure the base address for the console UART, the other
addresses are never assigned to the hardware. It seems better to
return 0 for them instead of a spurious value.

Change-Id: I3fa5c99958b56ca5b0b603917c086bdddb677fa2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-03 13:24:06 +00:00
Nico Huber 8bbad6c818 soc/intel/common/uart: Drop dead call to soc_uart_set_legacy_mode()
The only path that leads here is guarded by both !DRIVERS_UART_
8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects
the former.

Change-Id: I6e0765b028572950991c45b45b2051f4f176a94a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-03 13:23:55 +00:00
Nico Huber 51dc5ea735 soc/intel/common/lpss: Drop now unused lpss_clk_read()
Change-Id: I7def72e820ee1a4fa47c34b26dab9e0886ba74e6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-03 13:23:38 +00:00
Hung-Te Lin c345570acc src/driver/vpd: Update lib_vpd from upstream
Update lib_vpd.c (only containing vpd_decode.c) to latest version from
https://chromium.googlesource.com/chromiumos/platform/vpd

The called module (vpd.c) has been also corrected for new lib_vpd
types and constants.

BUG=chromium:967209
TEST=select VPD config on kukui; make; boots on at least kukui boards.

Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-06-03 13:22:01 +00:00
Nitheesh Sekar 6681f05373 qcs405: util/qualcomm: Add T32 debug scripts
Add T32 scripts that allow debug of any coreboot stage
on qcs405.

Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:20:38 +00:00
Jacob Garber f7f90f7c3f drivers/intel/fsp1_1: Exit cleanly if FSP not found
Instead of dereferencing a null pointer, print a nice message and exit
cleanly if the FSP isn't found in the CBFS.

Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401467, 1401717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:19:59 +00:00
Jacob Garber 7da638c20e mb/sifive/hifive-unleashed: Check for errors in fixup_fdt
It is possible that cbfs_boot_map_with_leak() and malloc() could fail,
so detect those conditions and print error messages if they do.

Change-Id: I34951da0b73028c4c89446cb1779a72422997325
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1399147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
2019-06-03 13:18:27 +00:00
Jacob Garber 38b7445ad2 mb/google/poppy/variants/nami: Add fallthrough comment
This fallthrough is intentional (see commit 2257a35862 - Perform PL2
setting for syndra), so add a comment to make that explicit.

Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1397063
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-03 13:18:11 +00:00
Arthur Heymans d44d4f0f4e mb/lenovo/*: Remove useless smihandler code
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.

Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33138
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:14:06 +00:00
Evgeny Zinoviev 60a0a3d629 ec/lenovo/h8: Fix method name in ACPI code
Fix a typo.

Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-03 10:10:21 +00:00
Nico Huber 2e6c3c8936 mb/google/link: Remove Link's own native graphics init
The code was already orphaned since its hook-up was removed
with a6be58fece (nb/intel/sandybridge: Remove the C native
graphic init).

Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-03 10:08:46 +00:00
Nico Huber ec93be5208 nb/intel/haswell/gma: Drop NGI remnant
The native graphics init option was replaced with libgfxinit.

Change-Id: I62569b70186b7b068effdadc4b39b3c09ddb7188
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33127
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:08:28 +00:00
Nico Huber d1b99d2bbf nb/intel/snb: Don't run VGA oprom when libgfxinit is enabled
This was likely an oversight when libgfxinit got its own Kconfig
symbols.

Change-Id: I647551719b332b5b734720ae4ee0619bbfcbed8c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33126
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:08:05 +00:00
Nico Huber bfd23ce87b soc/intel/common/mmc: Replace IS_ENABLED() with CONFIG()
Change-Id: I99d51176f6d7d6a98a3a3c82aa8e8eee73344496
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33111
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 10:05:55 +00:00
Matt DeVillier 0da3a8a91b soc/intel/baytrail: set default VBIOS filename and PCI ID
All Baytrail boards have the same GPU PCI ID, so set it
here to avoid having to set it in each board's config.

Move the VGA_BIOS_FILE config from google/rambi into soc/baytrail
since it likewise applies to all Baytrail boards.

Change-Id: Id1e0580b55e3590d868cb839987f06c49bb07cf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33026
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 22:26:34 +00:00
Matt DeVillier a82f991122 google/buddy: fix Windows ACPI error with WLAN
Buddy's WLAN ACPI code was equivalent to, but formatted
differently from the other auron variants. Since only
differnce is root port used, have buddy use common
WLAN ACPI and use preprocessor guards to set the root
port correctly.

Test: build/boot Buddy, verify Windows 10 boots
without ACPI BIOS ERROR.

Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30523
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 22:26:14 +00:00
Nitheesh Sekar a2c219a91d qcs405: Enable SPI-NOR
Enable support for Gigadevice spi-nor flash.

Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-02 19:52:37 +00:00
Patrick Georgi c82acf5931 qualcomm/qcs405: enable SPI bus 4 for TPM
Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-02 19:51:50 +00:00
Subrata Banik 2761847f90 Makefile.inc: Remove unnecessary CONFIG dependency
This patch removes unnecessary kconfig depencies as below
1. CONFIG_ARCH_RAMSTAGE_X86_32
2. CONFIG_RELOCATABLE_RAMSTAGE

Include required files as is without specify kconfig option.

Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-02 04:11:29 +00:00
Tim Wawrzynczak f3510cbe36 mainboard/google/hatch: Add Helios support
Add Helios as a variant of Hatch.

BUG=b:133182138
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
  attempts to build a Helios target.

Change-Id: I64ba06932eb0ee32405f7b14a94971a64c8fce71
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32918
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-31 18:54:14 +00:00
Tim Wawrzynczak cdc459e66a mb/google/hatch: Create helios variant
Created helios (hatch variant).  Currenly copied from kohaku.  Helios-
specific changes will come later.

BUG=b:133182138
BRANCH=none
TEST=none

Change-Id: I9d151621a1c42e6f3cadb288f7ea476828c059b5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-05-31 18:54:04 +00:00
Julius Werner a66c9b8bf4 string.h: Move common string functions into .c file
There's no clear reason why most of coreboot's basic string functions
are static inline. These functions don't particularly benefit from
inlining (at least not notably more than other functions). This patch
moves them to string.c to be more consistent with our usual coding
practices.

Leaving the ctype functions as static inline because they actually seem
small and collapsible enough that inlining seems reasonable.

Also clarified the situation of strdup() and strconcat() a bit more,
optimized strrchr() to be single-pass, fixed a bug with using strchr()
to find '\0' and got rid of unnecessary register keywords.

Change-Id: I88166ba9876e94dfa3cfc06969c78a9e1bc6fc36
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-05-31 18:22:11 +00:00
Paul Fagerburg 7fa3d5673c mb/google/hatch: Create kindred variant
Create the Kindred variant of Hatch by taking a copy of the Hatch files
as placeholders. Kindred-specific changes will happen in future CLs.

BUG=b:133181366
BRANCH=NONE
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_KINDRED

Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-31 15:28:25 +00:00
Furquan Shaikh a1d0928b00 soc/intel/common/block/gpio: Fix the mask for gpio_pm_configure
gpio_pm_configure clears out all the bits related to PM configuration
in MISCCFG register and sets only the bits requested by mainboard. The
mask as it is set currently results in preserving all PM bits instead
of clearing them. This change updates the mask to ensure that the PM
bits are cleared before setting the ones requested by mainboard.

Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-30 23:54:01 +00:00
Subrata Banik 695da71e61 src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.h
This patch fixes problem of adding CONFIG() check inside
rules.h.

Change-Id: Ifb6842d0efef3521642c5c399fdf2876f71b167a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-30 15:12:07 +00:00
Nico Huber d64f889972 mb/lenovo/*20*: Remove default FMAP
These boards don't need a default FMAP. Moreover, having a default FMAP
disables automatic integration of optional regions like `CONSOLE`.

Also, these files contain an error: `COREBOOT` isn't placed at the top
of the image. Resulting in default builds without a reset vector ;)

Change-Id: If6331e19955034c02828e88902a5934c34d3e784
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-30 14:57:59 +00:00
Nico Huber 10490b98e2 mb/roda/rk9: Document flash header
Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-30 13:46:41 +00:00
Patrick Georgi 2b99a01e0d soc/rockchip/rk3288: Disable bootblock console
Bootblock space is tight on this SoC and recent changes increased it
ever so slightly to make this a problem.

Since the bootblock is well-tested, we can get by without console.

Change-Id: I7496a3e313b2c6ee6fb3c4671eac64376d84e0dc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-30 03:46:20 +00:00
Damien Zammit 9b5e8c1718 xcompile: Remove --rtlib switch from clang CFLAGS
Fix the following error from clang invoking gcc linker with wrong arg:

i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1

Just remove --rtlib switch from CFLAGS relating to clang

Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29 20:33:35 +00:00
Patrick Rudolph a95a6bf646 libpayload/drivers/i8402/kbd: Fix qemu
Reset keyboard controller to fix qemu make scan codes.

Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29 20:32:44 +00:00
Elyes HAOUAS e39db681df src/mainboard: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.

Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29 20:29:28 +00:00