Commit Graph

39104 Commits

Author SHA1 Message Date
Julius Werner b652aaef99 cbfs: Skip mcache in post-RAM stages before CBMEM is online
There have been a few issues with the new CBFS mcache code in stages
after romstage, where the mcache resides in CBMEM. In a few special
cases the stage may be doing a CBFS lookup before calling
cbmem_initialize(). To avoid breaking those cases, this patch makes the
CBFS code fall back to a lookup from flash if CBMEM hasn't been
reinitialized yet in those stages.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icf6d1a1288cb243d0c4c893cc58251687e2873b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-08 21:38:57 +00:00
Julius Werner 364f9de149 cbmem: Make cbmem_online() accurate on stages after romstage
cbmem_online() always returns 1 in stages after romstage. However, CBMEM
isn't actually immediately available in those stages -- instead, it will
only become available when cbmem_initialize() is called. That usually
happens very early in the stage, but there are still small amounts of
code running beforehand, so it is useful to reflect this distinction.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I623c0606a4f49ea98c4c7559436bf32ebb83b456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-08 21:38:51 +00:00
Kevin Chang e38482610c mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration and disabling DDI port 1 and 2 HPD.
This patch adds the PMC MUX and CONx devices for lindar. Device
specific method contains the port and orientation details used
to configure the mux.

BUG=b:172533907
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-12-08 21:33:11 +00:00
Felix Singer 30fd5bffa2 soc/intel/cannonlake: Restore alphabetical order of Kconfig selects
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I5fa1e7216f3e80de0da5a58b84f221af321e4753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48396
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 21:16:59 +00:00
Felix Singer d49fafd531 mb/*: Remove SATA mode config for CNL based mainboards
SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.

Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08 21:16:51 +00:00
Felix Singer 1e3b2ce061 soc/intel/cannonlake: Align SATA mode names with soc/skl
Align the SATA mode names with soc/skl providing a consistent API.

Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08 21:16:30 +00:00
Felix Singer 77562cf95e mb/siemens/chili/base: Fix state of PCI devices
The PCI devices P2SB and PMC are hidden by the FSP and cannot be
unhidden, because the FSP locks their configuration. Thus, setting them
to `on` is not correct. Therefore, set their state to hidden.

Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 21:16:24 +00:00
Furquan Shaikh ae5f8a0751 Makefile: Allow platform to provide additional params for add cmd
This change adds optional CBFSTOOL_ADD_CMD_OPTIONS that can be used by
arch/SoC/mainboard Makefiles to supply any additional arguments that
need to be passed into cbfstool when using cbfstool add command.
This is useful when platform wants to add these parameters depending
upon some arch/SoC/mainboard specific configs. Immediate use case is
the fast SPI controller on Intel platforms adding arguments for
extended window base and size.

BUG=b:171534504

Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47884
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 21:15:48 +00:00
Felix Singer 78c3e1c50a mb/*: Remove SATA_AHCI config from SKL/KBL based devicetrees
SATA_AHCI is already the default mode for SKL/KBL based mainboards.
Therefore, remove its configuration from all related devicetrees.

Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48378
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:59:50 +00:00
Felix Singer d60abfcb74 soc/intel/skylake: Shorten SATA mode enum value names
The Skylake FSP isn't used by coreboot anymore. Therefore, drop the
misleading comment and the "KBLFSP" extension from the names of these
enums.

Also, drop the "MODE" extension to make their names shorter in general,
since it doesn't add any more value.

Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:50:27 +00:00
Felix Singer bd7020d68c soc/intel/skylake: Restore alphabetical order of Kconfig selects
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.

Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48376
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:50:13 +00:00
Felix Singer ad50856719 mb/clevo/l140cu: Use lower-case hex values
Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48375
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:50:05 +00:00
Felix Singer 0f0206c17c mb/siemens/chili: Remove unnecessary device declarations
Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08 20:49:54 +00:00
Felix Singer 8271cce959 mb/clevo/l140cu: Remove unnecessary device declarations
Remove unnecessary device declarations and remove comments where SMBIOS
slot descriptions are used.

Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:49:44 +00:00
Felix Singer e9da62a05f mb/clevo/l140cu: Use proper indents
Use proper indents in the devicetree and align `end` keywords.

Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:49:26 +00:00
Felix Singer aed8169ebb mb/clevo/l140cu: Make PCI devices P2SB and PMC hidden
The PCI devices P2SB and PMC are hidden by the FSP. So instead turning
them off, set their state to hidden being able to allocate ressources
for them.

Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 20:49:17 +00:00
Sheng-Liang Pan 9cce83c58e mb/google/volteer/var/voxel: Update DPTF parameters
remove TCC offset setting in overridetree.cb,
use default setting(# TCC of 90) in baseboard.

BUG=b:174547185
BRANCH=volteer
TEST=emerge-volteer coreboot

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 19:38:35 +00:00
Stanley Wu e9eecc902f mb/google/volteer: Update I2C5 bus freq and devicetree.
Update lindar gpio settings for Synaptics trackpad no function issue.
Update I2C5 bus freq to 400kHz.
Improve Goodix Touchscreen power on sequence.

BUG=b:160013582
BRANCH=firmware-volteer-13521.B
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device. Verify trackpad function workable.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-08 19:32:26 +00:00
Furquan Shaikh f5b30eda1f commonlib/region: Allow multiple windows for xlate_region_dev
This change updates the translated region device (xlate_region_dev) to
support multiple translation windows from the 1st address space to
2nd address space. The address spaces described by the translation
windows can be non-contiguous in both spaces. This is required so that
newer x86 platforms can describe memory mapping of SPI flash into
multiple decode windows in order to support greater than 16MiB of
memory mapped space.

Since the windows can be non-contiguous, it introduces new
restrictions on the region device ops - any operation performed on the
translated region device is limited to only 1 window at a time. This
restriction is primarily because of the mmap operation. The caller
expects that the memory mapped space is contiguous, however, that is
not true anymore. Thus, even though the other operations (readat,
writeat, eraseat) can be updated to translate into multiple operations
one for each access device, all operations across multiple windows are
prohibited for the sake of consistency.

It is the responsibility of the platform to ensure that any section
that is operated on using the translated region device does not span
multiple windows in the fmap description.

One additional difference in behavior is xlate_region_device does not
perform any action in munmap call. This is because it does not keep
track of the access device that was used to service the mmap
request. Currently, xlate_region_device is used only by memory mapped
boot media on the backend. So, not doing unmap is fine. If this needs
to be changed in the future, xlate_region_device will have to accept a
pre-allocated space from the caller to keep track of all mapping
requests.

BUG=b:171534504

Change-Id: Id5b21ffca2c8d6a9dfc37a878429aed4a8301651
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47658
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 18:59:18 +00:00
Furquan Shaikh 73982edadd util/cbfstool/fmaptool: Generate list of terminal sections
This change adds support in fmaptool to generate a macro in C header
file that provides a list of section names that do not have any
subsections. This is useful for performing build time tests on these
sections.

BUG=b:171534504

Change-Id: Ie32bb8af4a722d329f9d4729722b131ca352d47a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-08 18:59:05 +00:00
Furquan Shaikh 0ae389cb23 util/cbfstool: Add support for mapping extended window for x86 platforms
All x86 platforms until now have memory mapped up to a maximum of
16MiB of SPI flash just below 4G boundary in host address space. For
newer platforms, cbfstool needs to be able to accommodate additional
windows in the host address space for mapping SPI flash size greater
than 16MiB.

This change adds two input parameters to cbfstool ext-win-base and
ext-win-size which a platform can use to provide the details of the
extended window in host address space. The extended window does not
necessarily have to be contiguous with the standard decode window
below 4G. But, it is left upto the platform to ensure that the fmap
sections are defined such that they do not cross the window boundary.

create_mmap_windows() uses the input parameters from the platform for
the extended window and the flash size to determine if extended mmap
window is used. If the entire window in host address space is not
covered by the SPI flash region below the top 16MiB, then mapping is
assumed to be done at the top of the extended window in host space.

BUG=b:171534504

Change-Id: Ie8f95993e9c690e34b0e8e792f9881c81459c6b6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47882
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 18:58:57 +00:00
Furquan Shaikh 0dcc0662f3 util/cbfstool: Introduce concept of mmap_window
This change adds the concept of mmap_window to describe how the SPI
flash address space is mapped to host address space on x86
platforms. It gets rid of the assumption that the SPI flash address
space is mapped only below the 4G boundary in host space. This is
required in follow up changes to be able to add more decode windows
for the SPI flash into the host address space.

Currently, a single mmap window is added i.e. the default x86 decode
window of maximum 16MiB size living just below the 4G boundary. If the
window is smaller than 16MiB, then it is mapped at the top of the host
window.

BUG=b:171534504
TEST=Verified using abuild with timeless option for all coreboot
boards that there is no change in the resultant coreboot.rom file.

Change-Id: I8dd3d1c922cc834c1e67f279ffce8fa438d8209c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-08 18:58:06 +00:00
Furquan Shaikh 19ba95f799 util/cbfstool: Rename IS_TOP_ALIGNED_ADDRESS to IS_HOST_SPACE_ADDRESS
This change renames the macro `IS_TOP_ALIGNED_ADDRESS` to
`IS_HOST_SPACE_ADDRESS` to make it clear that the macro checks if
given address is an address in the host space as opposed to the SPI
flash space.

BUG=b:171534504

Change-Id: I84bb505df62ac41f1d364a662be145603c0bd5fa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47830
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 18:57:35 +00:00
Furquan Shaikh 6b6e9b503d util/cbfstool: Treat region offsets differently than absolute addresses
cbfstool overloads baseaddress to represent multiple things:
1. Address in SPI flash space
2. Address in host space (for x86 platforms)
3. Offset from end of region (accepted as negative number)

This was done so that the different functions that use these
addresses/offsets don't need to be aware of what the value represents
and can use the helper functions convert_to_from* to get the required
values.

Thus, even if the user provides a negative value to represent offset
from end of region, it was stored as an unsigned integer. There are
special checks in convert_to_from_top_aligned which guesses if the
value provided is really an offset from the end of region and converts
it to an offset from start of region.

This has worked okay until now for x86 platforms because there is a
single fixed decode window mapping the SPI flash to host address
space. However, going forward new platforms might need to support more
decode windows that are not contiguous in the host space. Thus, it is
important to distinguish between offsets from end of region and
addresses in host/SPI flash space and treat them separately.

As a first step towards supporting this requirement for multiple
decode windows on new platforms, this change handles the negative
offset provided as input in dispatch_command before the requested cbfs
operation is performed.

This change adds baseaddress_input, headeroffset_input and
cbfsoffset_input to struct param and converts them to offsets from
start of region before storing into baseaddress, headeroffset and
cbfsoffset if the inputs are negative.

In follow up changes, cbfstool will be extended to add support
for multiple decode windows.

BUG=b:171534504
TEST=Verified using abuild with timeless option for all coreboot
boards that there is no change in the resultant coreboot.rom file.

Change-Id: Ib74a7e6ed9e88fbc5489640d73bedac14872953f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47829
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 18:57:24 +00:00
Jes Klinke 6e929acb73 mb/google/volteer: ACPI nodes for volteer2_ti50
Unique among the Volteer devices, the volteer2_ti50 variant connects to
the TPM via I2C.  This CL introduces the proper devicestree declarations
for the Linux kernel to recognize that.

overridetree.cb is shared between "sub"-variants volteer2 and
volteer2_ti50, so both will have two TPM nodes, the I2C being disabled
by default.  The odd _ti50 variant then has code in variant.c to enable
the I2C node and disable the SPI node.

BUG=b:173461736
TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x

Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 16:59:37 +00:00
Sumeet R Pawnikar a97fb7f960 mb/google/volteer/variants: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value for
volteer variants like baseboard, delbin, eldrid, terrador and todor.
All other variants uses the DTT entries from baseboard devicetree since
there is no override present for those variants. DTT does not throttle PL2,
so this minimum value change here does not impact any existing behavior on
the system.

BUG=None
BRANCH=volteer
TEST=Build and test on volteer system

Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08 16:56:29 +00:00
Kaiyen Chang 62d73b6be5 soc/intel/common/gpio_defs: Add PAD_TRIG(OFF) in PAD_CFG_GPI_GPIO_DRIVER
Probabilistic interrupt storm is observed while kernel is configuring
the GPIO for SD card CD pin. The root cause is that the macro
PAD_CFG_GPI_GPIO_DRIVER isn't configuring trigger as PAD_TRIG(OFF).

The way GPIO interrupts are handled is:
1. Pad is configured as input in coreboot.
2. Pad IRQ information is passed in ACPI tables to kernel.
3. Kernel configures the required pad trigger.

Therefore, PAD_TRIG(OFF) should be added in PAD_CFG_GPI_GPIO_DRIVER
to turn off the trigger while pad is configured as input in coreboot
and then let kernel to configure the required pad trigger.

BUG=b:174336541
TEST=Run 1500 reboot iterations successfully without any interrupts
     storm.

Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Change-Id: Icc805f5cfe45e5cc991fb0561f669907ac454a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-12-08 16:56:00 +00:00
Jes Klinke f99f589ea9 drivers/i2c/tpm: Unconditionally allow I2C TPM ACPI node
DRIVER_I2C_TPM_ACPI is used to enable the "driver" needed for coreboot
to present a TPM node in the devicetree.  It would usually only do so,
if coreboot itself is communicating with the TPM via I2C (I2C_TPM).
However, technically, there is no dependency.

In order to not show the ACPI option in menuconfig if the board is not
using I2C, a dependency was declared in Kconfig.  However, the same can
be achieved without making it an error to manually declare
DRIVER_I2C_TPM_ACPI without I2C_TPM.

For Volteer, we have just such a need, since it has two "sub-variants"
sharing the same overridetree.cb, one having SPI TPM and another having
I2C TPM.  The former will have a disabled ACPI node representing the I2C
TPM, while its Kconfig is such that coreboot itself does not have I2C
TPM support.

In order to export even a disabled ACPI node representing the I2C
connected TPM, coreboot needs DRIVER_I2C_TPM_ACPI.  Hence, that will
have to be enabled in a case where coreboot does not have I2C_TPM (for
one of the two sub-variants, namely volteer2).

BUG=b:173461736
TEST=Tested as part of next CL in chain

Change-Id: I9717f6b68afd90fbc294fbbd2a5b8d0c6ee9ae55
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48222
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 16:54:56 +00:00
Felix Held 9a1583b030 MAINTAINERS: add maintainers for AMD family 17h and 19h reference boards
Change-Id: I90673a3244c5f2d5eda8e8805779fdad3a2b3226
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-08 14:53:55 +00:00
Subrata Banik 3e6cfa268c soc/intel/common/usb4: Add ADL-P DMA0/1 ID into USB4 common code
Change-Id: Id014828d282350bcb1f4de295d5cfb72b6950634
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-08 06:37:44 +00:00
Subrata Banik 89b296c3fe soc/intel/common/block/cpu/car: Fix two whitespace issues
This patch removes 1 unnecessary whitespace and add 1 whitespace into IA
common car code block.

Change-Id: I3690b5f219f5326cfca7956f21132062aa89648e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-08 06:37:06 +00:00
Angel Pons cdd9db340b nb/intel/ironlake: Introduce memmap.h
Move all memory map definitions into a separate header.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45379
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07 15:58:55 +00:00
Angel Pons 1110b2f462 nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
There's no need to wrap these macros with casts. Removing them allows
dropping more casts in `early_init.c`.

To avoid binary changes the casts are put into the
{MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach
the right memory locations.

Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07 15:24:20 +00:00
Patrick Georgi 02a23b510c nb/intel/i945: Introduce memmap.h
Inspired by Idca25b2e4bf65abcb and Ib275f9ad8ca9ff move all memory map
definitions into a header with a common name.

Change-Id: I32a99f70f4d2eb52367c9edfc0aa6d5da2fec03f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-07 14:19:51 +00:00
Michael Niewöhner 88e85b3de4 soc/intel/skl: set PEG port state to auto
Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.

Note: Currently, this only works with the AST PCI bridge disabled or the
      VGA jumper set to disabled on coreboot, while it works on vendor
      in any case. The reason for this is still unclear.

Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
      instead of just PC3

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-07 14:07:17 +00:00
Sridhar Siricilla 416b828f47 sb/intel/common: Modify CONFIG_LOCK_MANAGEMENT_ENGINE behavior
The patch modifies KConfig behaviour if CSE Lite SKU is integrated into
the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents
writing to ME region but keeps read access enabled. Since CSE Lite driver
checks the signature of RW partition to identify the interrupted CSE
firmware update, so host must have read access to the ME region. Also, the
patch modifies the KConfig's help text to reflect the change.

When CSE Lite SKU is integrated, master access permissions:
FLMSTR1:   0x002007ff (Host CPU/BIOS)
  EC Region Write Access:            disabled
  Platform Data Region Write Access: disabled
  GbE Region Write Access:           disabled
  Intel ME Region Write Access:      disabled
  Host CPU/BIOS Region Write Access: enabled
  Flash Descriptor Write Access:     disabled
  EC Region Read Access:             disabled
  Platform Data Region Read Access:  disabled
  GbE Region Read Access:            disabled
  Intel ME Region Read Access:       enabled
  Host CPU/BIOS Region Read Access:  enabled
  Flash Descriptor Read Access:      enabled

BUG=b:174118018
TEST=Built and verified the access permissions.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-12-07 14:06:28 +00:00
Wisley Chen e02b62a4f5 mb/google/volteer/var/elemi: use devtree aliases for PMC MUX connectors
refer to cb:45878
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.

BUG=b:174735512
BRANCH=volteer
TEST=build and type-c display work

Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07 14:03:10 +00:00
Arthur Heymans 38e1f736dd util/cbfstool/.gitignore: Add ifittool
Change-Id: Ie0ee6511e91c0bf1ff2f4ca49b24e3e5a36a06f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-12-07 14:02:38 +00:00
V Sowmya 1369516d28 common/block/cse: Rename cbfs_boot_load_file() to cbfs_load()
This patch renames the cbfs_boot_load_file() to cbfs_load() to
avoid the build errors for cselite and align with the new changes
to API https://review.coreboot.org/c/coreboot/+/39304 .

Change-Id: I717f0a3291f781cc3cf60aae88e7479762ede9f9
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07 11:53:13 +00:00
Johnny Lin 6ebfee848c vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB
Tested=On OCP Delta Lake, verify the memory map hob data are correct.

Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-07 10:30:09 +00:00
Meera Ravindranath 290b434d64 mb/intel/adlrvp: Remove GPP_E0
Remove the unused UART_BT_WAKE GPIO as BT is over USB.

Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-07 06:24:12 +00:00
Felix Held 36d1e01b21 soc/amd/picasso: drop unused cpu/amd/mtrr from Makefile
TEST=Timeless build of mb/amd/mandolin results in identical image.

Change-Id: Ib1337f64ea7057cf04ca92bdef66e35cc350625d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06 20:10:11 +00:00
Felix Held c8272783db soc/amd/cezanne: add config.c and minimal chip.h
Change-Id: I89f08c201bd7d9a11b186ef960abe9714a76fb97
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06 19:05:47 +00:00
Felix Held 04f079d396 soc/amd/picasso/config: add comment about cfg never being NULL
Change-Id: I39cf2d28749536cb7d9462fa4af412850677f2e3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06 19:04:51 +00:00
Felix Held 507fc03b19 soc/amd/picasso: remove config_t typedef
Change-Id: Idc0061e7b88134ab17cb65429133cffd16ca5651
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06 19:04:33 +00:00
Felix Held 0f058f68a2 soc/amd/picasso/chip.h: remove unneeded extern pci_domain_ops
Now pci_domain_ops in chip.c can also be marked as static.

Change-Id: Ia92b778a5882d991b391dc29aeee0a5615677913
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48315
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06 19:03:40 +00:00
Felix Held 49f6b9d05b soc/amd/stoneyridge: remove unused config_t typedef
Change-Id: I1456fe069c4b0cf859f769e0144ec62cff0f3987
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06 19:02:42 +00:00
Felix Held d28e159fdf soc/amd/stoneyridge/chip.h: remove unneeded extern pci_domain_ops
Now pci_domain_ops in chip.c can also be marked as static.

Change-Id: I5e481fe311c9db4aacfd94bbf671edf679528946
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06 19:01:44 +00:00
Felix Held f824a9be0b soc/amd/stoneyridge/acpi/sb_fch: use existing base address defines
TEST=Identical timeless build for amd/gardenia.

Change-Id: I04952cdbbe7893f35a674a156a9bc22202fbdc2f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06 19:01:12 +00:00
Felix Held f914dcf3dd include/device/device: add comment that config_of_soc never returns NULL
Since config_of() calls die() if dev or dev->chip_info are NULL,
config_of_soc() will either return a non-NULL pointer or won't return.

Change-Id: I6de6bb1610e823af215436c94ff1a78ff6b86b78
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-12-06 19:00:35 +00:00