We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.
The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS. In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.
BUG=b:74200887
TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and
"earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
command line, and with an image with serial console enabled.
=> System boots with (kernel) serial console enabled, starting from
0.00 (earlycon), with no gaps in its output, and serial console
also allows logging in.
Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after
initialization of cs polarity since it requires polarity to be
set to work properly. Failure to do so confuses cr50.
BUG=b:70628116
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' and verify on scope that chip select
polarity is correct for the first transaction.
Change-Id: I20b4f584663477d751a07889bccc865efbf9c469
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
coreboot's PCI resource allocator doesn't assign BAR1 for
Braswell's LPE device because it doesn't exist, but is
required by Windows drivers for the device to function.
Manually add the required resource via the existing
lpe_read_resources function, and marked it as IORESOURCE_STORED
so pci_dev_set_resources ignores it.
TEST: boot Windows 10 on google/edgar, observe that memory resources
are properly assigned to LPE driver for BAR1 and no error reported.
Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add timestamps before and after the vBIOS load and after the vBIOS
run. This lets us see exactly how long it took to load it from the
ROM chip, and how long it takes to run.
BUG=b:64549506
TEST=Build & boot Grunt, see vBIOS load & initialization times.
Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25018
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hardware updates have suggested we need to configure the K&D panel's
power sequence in software, not in hardware. Without this change, K&D
panels will no longer power on correctly and will instead display a
black screen.
Per K&D's suggestion, we tweak these two commands. From the little HW
docs I have, this looks like it's:
(Address 0xB7, Value 0x02) -> set BC_CTRL=bit(1) (Back light control) to
1
(Address 0xF1, Value 0x22) -> change GPO2_SEL=bits(0:3) from
MIPI_TE(0001b) to BC_CTRL (0010b)
BRANCH=scarlet
BUG=b:73133861
TEST=KD display with and without HW fix on Scarlet
Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/25023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like there's a typo in the GPIO state table we print as part of
assembling the coreboot tables. Of course, high GPIOs are represented as
1 and low GPIOs as 0. Fix this display bug.
Change-Id: I59b4d49955c13f920576dd09f463e2d399ab64e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Allows eMMC in PCI mode to be seen/used by Windows.
Test: boot Windows installer on google/edgar, observe internal
eMMC storage available for installation when eMMC in PCI (vs ACPI) mode.
Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch configures the gpios for all the gpio communites.
Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Per vendor datasheet, corrected linkfreq of imx258 as
{633600000, 320000000}
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/24990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We want to report the board SKU via the SMBIOS tables. Add support for
this, obtaining the ID itself from the EC.
BUG=b:74175244
BRANCH=none
TEST=manually on grunt with another CL:
mosys platform sku
0
Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.
BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).
Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The LPEA device memory resources, required by Windows drivers,
were not being set. Allocate required resources per Inte'sl CHT
Tianocore reference code.
Test: boot Windows on google/edgar, observe LPEA device working properly.
Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Certain platforms need paging enabled during cache-as-ram because
dirty lines are being evicted by a heavy speculative frontend. Paging
needs to be enabled in order to utilize the NX (no execute) bit for
the regions that are strictly data (such as the stack). This utility
creates 32-bit PAE page tables using a static address space, and
the resulting tables have entries for all the PDPTEs such that it makes
it easy to enable 2MiB naturally aligned DRAM mappings once memory is
trained. Either binary files can be generated or C files. The pages that
are linked use a default base address of 0xaa000000 that can be changed at
runtime to reflect where the page tables are actually loaded. Or
specify a physical address on the command line that is known a priori.
iomap.txt:
0xd0000000, 0x100000000, UC, NX # All of MMIO
0xff000000, 0x100000000, WP, # memory-mapped SPI
0xffff8000, 0x100000000, WP, # XIP bootblock
0xfef00000, 0xfefc0000, WB, NX # CAR
0xfef40000, 0xfefc0000, WB, # verstage
0xfef20000, 0xfefc0000, WB, # romstage
0xfef40000, 0xfefc0000, WB, # fsp-m
$ go run util/x86/x86_page_tables.go --iomap_file=iomap.txt
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 UC NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xaa000000.
BUG=b:72728953
Change-Id: I47625a24979b196011e2293712a8cdbdbb880d79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/24919
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done by overriding the weak functions from smbios.c
Some values are hardcoded as they are characteristics of the
Tagada system. Other are retrieved from the BMC through the
bmcinfo interface.
Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23843
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add more information on baseboard as described in SMBIOS Reference
Specification 3.1.1.
Change-Id: I9fe1c4fe70c66f8a7fcc75b93672421ae808bf1b
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This interface gives access to configuration information stored in flash
by the Tagada BMC before booting the SoC.
Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO.
BUG=b:73514687
BRANCH=None
TEST=None
Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add spd files for LPDDR3 based on info received from factory team.
BUG=b:73287172
BRANCH=None
TEST=None
Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Limit dependency on vendorcode header files and use defines from
iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.
BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt
Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Increase memory allocated for the LPEA firmware from 1MiB to 2MiB
to match Intel CHT reference code and fix Windows functionality.
Test: boot Windows on google/edgar, observe no error in Device Manager
for LPEA audio device due to BAR2 resource allocation.
Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Without PMAX correctly set, the calculation for PLEN is incorrect,
leading to a Windows BSOD on boot. Correct PMAX using code from
Baytrail SoC, setting PMAX to (CONFIG_MMCONF_BASE_ADDRESS - 1).
Test: Boot Windows 10 on google/edgar without BSOD.
Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24985
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some type-c monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Also, if an HDMI monitor is connected, no wait is needed. If only
an HDMI monitor is connected, currently the API always loops until
the stopwatch expires.
This patch will make the AP skip DisplayPort wait loop if it detects
an HDMI monitor. And if an HDMI monitor is not detected, the AP will
wait for DisplayPort mode (like before) but also its HPD signal.
This patch also extends the wait loop time-out to 3 seconds.
BUG=b:72387533
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The MMCONF base address and length are set in Kconfig so it does
not need to be redefined by the SOC as the code can just use the
Kconfig variable directly.
Tested on a fizz board to ensure MCFG is still created properly.
Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24975
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI MCFG table is generated with a static end bus number of 255,
which expects that the reserved range in E820 is 256MB. However the
actual MCFG range is configurable with Kconfig, so these two values
may not match when the OS tries to determine the range:
PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!)
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
Instead of forcing the end bus number to be 255 use the Kconfig value
to set it based on the current configuration.
Tested on a fizz device to ensure that the kernel no longer complains:
PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)
Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24974
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot
and should not be used as a UART device. coreboot is setting the
pins to GPIO Mode but FSP is re-configuring them for Native Mode
and the behavior is unexpected when the kernel tries to initialize
the UART device.
The UART 0 device is PCI function 0 so it needs to be enabled for
other functions to be visible to the OS so it can't just be disabled.
Instead, set the device to PchSerialIoSkipInit so that FSP will not
change the pin state.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware to ensure the pin state
does not change when FSP runs or the kernel boots.
Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SMBus PCI device ID for Stoney wasn't updated when the code was
pulled over from hudson. This means that the IOAPIC wasn't being
initialized in coreboot.
BUG=b:74070580
TEST=Boot Grunt, see IOAPIC init messages in console.
Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/24930
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 2e81f394cf, as it will
have side effect that will make system shutdown failure. System will not
enter S5 sleep state, instead a global reset will be generated.
Once camera driver ACPI framework ready, isclk programing will be moved
into APCI method, in _PS3, isclk will be turned off to save power.
BUG=b.72532565
BRANH=master
TEST=Apply the changes and flash coreboot, on meowth devices, issue
"halt" in OS stage, system can shutdown successfully.
Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 1dfc2c3
[google/chromeec: Enable unified host event programming interface]
added support for UHEPI, but google_chromeec_is_uhepi_supported()
incorrectly treats negative error return codes from
google_chromeec_check_feature() as supported. Fix this check to only
treat positive return values as supported, as per the original intent.
Test: boot google/lulu, verify cbmem console reports UHEPI not
supported even if feature check returns error code, verify lid/kb
wake events correctly wakes the device from S3/sleep.
Change-Id: I7846efb340bc1546b074e8502daf906c444bd146
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for variants to use secondary SPD if
required. This enables a variant to have different types of memory
supported using the same image.
BUG=b:73514687
Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Similar to Soraka, this change sets the pch_trip_temp value to
75C. This is important so that PMC can shutdown the thermal sensor
when CPU is in C-state and DTS temp <= pch_trip_temp.
BUG=b:74089135
Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, the AP check-in time-out in bsp_do_flight_plan is set to
100ms. However, as the number of APs increases, contention could
increase especially for resource like UART. This led to MP record
time-out issues on KBL platform with 7 APs and serial-console enabled
BIOS image.
This change increases the time-out value to 1 second to be on the safer
side and let APs check-in before continuing boot.
BUG=b:74085891
TEST=Verified that MP record time-out is not observed anymore on Nami.
Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a configurable delay in milliseconds before SLP_EN is set in
SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power
button SMIs.
On some platforms (Nami, Nautilus), it was observed that power button SMI
triggered by EC was competing with the SLP SMI triggered by keyboard
driver. Keyboard driver indicated power button press which resulted in
depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power
button press also causes the EC to send a pulse on PWRBTN# line, which is
debounced for 16ms before an interrupt is triggered. This interrupt was
generated after SLP_SMI is processed which resulted in the device waking back up
from S5.
This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is
used to add a delay before SLP_EN is set for S5. This change should only affect
CHROMEOS boards as the config option will be 0 in other cases.
BUG=b:74083107
TEST=Verified that nami, nautilus do not wake back from S5 on power button press
at dev mode screen.
Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is useful information, when debugging problems related to graphics.
Change-Id: Iacb0ae5f012207192379fd07e91f4687ec32cdfb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23807
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Shelley Chen