Commit Graph

6651 Commits

Author SHA1 Message Date
Patrick Georgi 552c45cf1f Finally update 3rdparty
Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1242
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-19 13:58:02 +02:00
zbao 7a6bdd213a Add missing quote.
Remove the menuconfig warning which comes up every time.
src/mainboard/asus/Kconfig:85:warning: multi-line strings not supported

Change-Id: I0ec0a0b625a33edd1d9b250a26aa3e0f42142eca
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1240
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-19 08:01:01 +02:00
Kyösti Mälkki 07284633d8 AMD northbridges: drop dead code
Change-Id: I03949722ac3a127319a0ad3f812d77ba7b8f139f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1187
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-18 10:31:08 +02:00
Mathias Krause 41c229c029 cbfstool: signed vs. unsigned fixes
Use the right data types to fix compiler warnings.

Change-Id: Id23739421ba9e4a35599355fac9a17300ae4bda9
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1236
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:35 +02:00
Mathias Krause 5c581c4d6c cbfstool: provide a prototype for remove_file_from_cbfs
To complement commit e1bb49e (Add a "remove" command to cbfstool) and
fix a compiler warning provide a prototype for remove_file_from_cbfs.

Change-Id: Ied8eac956de5fed3f9d82ce1e911ee1fec52db15
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1235
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:27 +02:00
Mathias Krause d2567c8d92 cbfstool: make endian detection code more robust
Accessing the memory of a char array through a uint32_t pointer breaks
strict-aliasing rules as it dereferences memory with lower alignment
requirements than the type of the pointer requires. It's no problem on
x86 as the architecture is able to handle unaligned memory access but
other architectures are not.

Fix this by doing the test the other way around -- accessing the first
byte of a uint32_t variable though a uint8_t pointer.

Change-Id: Id340b406597014232741c98a4fd0b7c159f164c2
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/1234
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-07-18 00:15:15 +02:00
Kyösti Mälkki 1171986627 Drop invalid device ops on Agesa northbridge
One could not pass a device of type APIC to PCI resource functions.
The correct CPU model specific cpu->ops is set at later time in
cpu_initialize().

Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 20:33:59 +02:00
Kyösti Mälkki de3dde46fd AMD: Fix GFXUMA with 4GB or more RAM
Northbridge code incorrectly adjusted the last cacheable memory
resource to accomodate room for UMA framebuffer. If system had
4GB or more memory that last resource is not below 4GB and not
the one where UMA is located.

There are three consequences:

The last entry in coreboot memory table is reduced by uma_memory_size.

Due the incorrect code in northbridge code state.tomk,
end of last resource below 4GB, had not been adjusted.
Incrementing that by uma_memory_size diverts a region
possibly claimed for MMIO to RAM, as TOP_MEM is written.

Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
it was ignored from the MTRR setup and not set uncacheable.

The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
should be copied from BSP to all APs instead of deriving the data
separately for each Logical CPU.

Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1217
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:57:43 +02:00
Kyösti Mälkki 2354515f2e AMD MTRR: fix rounding and renames
Use state.tomk to refer TOP_MEM, largest RAM address below 4GB.
Use state.tom2k to refer TOP_MEM2, largest RAM address above 4GB.

When setting either TOP_MEM or TOP_MEM2, any RAM resource found
must fit below the set value. Thus, round register value upwards,
not downwards.

Change-Id: I436c1b3234c911680ce8b095052f8d71f40113e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1216
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:55:34 +02:00
Kyösti Mälkki 2d42b34003 Check for IORESOURCE_UMA_FB in MTRR setup
If northbridge called uma_resource() a resource of this type
should be found when walking the resources list.

For now, be rude and don't even try to combine it with
neighboring regions. As the type is un-cacheable it is
dominant over other MTRR setups claiming the same region.

Change-Id: I57805e7e7da0709f8ed78d8df62c2abf22172a06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:54:34 +02:00
Kyösti Mälkki 0b08515c2b Change uma_resource() to use new type IORESOURCE_UMA_FB.
MTRR setup code can detect this and mark it as UC/WT/WC as suitable
for the specific hardware.

Change-Id: Ib7a3d450fc7c19e3ca72767dfb350412dd35c971
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1214
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:51:30 +02:00
Kyösti Mälkki ba589e3630 Move setup_uma_memory() to K8 northbridge
These boards had identical UMA code:
  amd/dbm690t
  amd/pistachio
  technexion/tim5690
  technexion/tim8690

The ones below had whitespace or debug level change
compared to the one above:
  kontron/kt690
  siemens/sitemp_g1p1

These boards use AMDFAM10 guidelines in code:
  asrock/939a785gmh
  amd/mahogany

Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:46:33 +02:00
Kyösti Mälkki 231f261402 Move setup_uma_memory() to AMDFAM10 northbridge
Following boards had identical code:
  advansus/a785e-i
  amd/bimini_fam10
  amd/mahogany_fam10
  asus/m5a88-v
  avalue/eax-785e
  gigabyte/ma78gm
  iei/kino-780am2-fam10
  jetway/pa78vm5

Following boards had identical code:
  amd/tilapia_fam10
  asus/m4a78-em
  asus/m4a785-m
  gigabyte/ma785gm
  gigabyte/ma785gmt

In between the two, only whitespace difference.

Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:45:37 +02:00
Kyösti Mälkki 55fff930ce Move setup_uma_memory() to Agesa Family14 northbridge
Following boards had identical code:
  amd/inagua
  amd/persimmon

The following had only whitespace or debug level changes
compared to ones above.
  amd/union_station
  amd/south_station
  asrock/e350m1

Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:45:09 +02:00
Kyösti Mälkki d4821fc702 Move setup_uma_memory() to Agesa Family12 northbridge
Change-Id: Ieaf284c207f0cd4b2f6b804c52f949c16435d823
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:44:29 +02:00
Kyösti Mälkki 03548aa6b8 Move setup_uma_memory() to Agesa Family15 northbridge
Change-Id: I5705623f5067823fae5986b3bcde58504a463508
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:43:35 +02:00
Kyösti Mälkki cc55b9b919 Define global uma_memory variables
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.

It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.

Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:41:46 +02:00
Kyösti Mälkki 63f8c08830 Add global uma_resource()
Like ram_resource(), but reserved and not cacheable.

Switch all AMD northbridges to use this one.

Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:38:46 +02:00
Sven Schnelle d4220691c5 i5000: Fix resource allocation
The current code didn't reserve static resource the right way.
Also reduce TOLM to 0xd0000000, because those boards have so many PCI
devices that 0xe0000000 isn't sufficient.

Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1220
Tested-by: build bot (Jenkins)
2012-07-16 08:40:48 +02:00
Ronald G. Minnich f8878845f9 Poison the stack to uncover programming errors
Code can easily make the mistake of using uninitialized
values or, in assembly, mistakenly dereferencing stack pointers
when an address is desired.

Set the stack to a non-zero value which is also (by testing)
a pointer which will crash coreboot if used. This poisoning
has uncovered at least one bug.

Change-Id: I4affb9a14b96611e8bf83cb82636e47913025a5d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1221
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-15 11:01:01 +02:00
Sven Schnelle 2d0d83c3dd Add ASUS DSBF mainboard
Change-Id: Iad38b92ca3a582e5aec07b92c994bfbe78b09855
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1223
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14 17:34:57 +02:00
Sven Schnelle 6fa1d3a218 Supermicro X7DB8: Use autogeneration of mptable
And fix the wrong indenting of devicetree.cb while at it.

Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1222
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14 17:31:13 +02:00
zbao 246e84bc0d AGESA F15 wrapper for Hudson.
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper.

Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14 16:29:52 +02:00
zbao 22b7a55a4d Remove useless file from building.
Change-Id: I09c695347c04d7db9add2cbb687d59c829175cfc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1224
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14 16:28:10 +02:00
Patrick Georgi 2b108a4368 sconfig: fix up shipped code
The lex compile wasn't current (or something) and so INTA wasn't lexed
properly.

Change-Id: I5a760430788792f54c4e1e0d419b8dd525079d15
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1226
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-13 20:27:28 +02:00
Christian Gmeiner 86f992c38a Add preliminary support for Bachmann electronic OT200
Linux boots fine :)

Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1225
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 14:34:31 +02:00
Christian Gmeiner 42b808e889 msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e)
This register is helpful for porting new mainboards based on
cs5536 southbridge.

Change-Id: Iff3adc2c2fbc672c8541096756f95b3322f6ab19
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1211
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 08:40:14 +02:00
Sven Schnelle 0fa50a1990 MPTAPLE: generate from devicetree.cb
This patch adds support for autogenerating the MPTABLE from
devicetree.cb. This is done by a write_smp_table() declared
weak in mpspec.c. If the mainboard doesn't provide it's own
function, this generic implementation is called.

Syntax in devicetree.cb:

ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN>

The ioapic_irq directive can be used in pci and pci_domain
devices. If there's no directive, the autogen code traverses
the tree back to the pci_domain and stops at the first device
which such a directive, and use that information to generate the
entry according to PCI IRQ routing rules.

Change-Id: I4df5b198e8430f939d477c14c798414e398a2027
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1138
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 08:38:13 +02:00
Sven Schnelle 6591470ae0 IOAPIC: hook up driver in Kconfig
Missed to add the driver to Kconfig and Makefile.inc.

Change-Id: I64b02abc5de2f6483f610436ebb38a7ca433f9b6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1219
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-13 08:38:08 +02:00
Kyösti Mälkki ffc1fb35aa Drop Kconfig VAR_MTRR_HOLE option
All but one board use the default value of enabled. Disabling
this can only increase the number of MTRR registers used.

Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12 20:28:35 +02:00
Anton Kochkov db2c400ab8 libpayload: Add reset function for OHCI USB driver
Implemented OHCI reset function ohci_reset() in ohci.c
for libpayload's USB driver.

Change-Id: Id6518cbe00a21202757b34926bad171909740e97
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1177
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12 10:00:17 +02:00
Jonathan A. Kollasch 25962837ba Lenovo X60: correct SDHCI write protect polarity
Change-Id: I916deffe2c692042f7e54c936902e77770ee69df
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/1205
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-12 08:16:17 +02:00
Guenter Roeck 21856eec59 superiotool: Dump data registers for Nuvoton chips
Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F,
and NCT6779D). Register contents will be dumped if the -e option is provided on
the command line.

Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1150
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12 08:13:21 +02:00
Guenter Roeck a89da0969e superiotool: Add support for function to dump superio chip data registers
Add new function dump_data() to dump a bank of superio data registers.

Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1149
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12 08:13:13 +02:00
Guenter Roeck 975ffc2e0f superiotool: Add support for NCT6775F(A/B) and NCT6779D
Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-on: http://review.coreboot.org/1148
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12 08:10:28 +02:00
Sven Schnelle 6f73a5bf70 Fix stack assignment during CPU initialization
There are two errors in the code. The first one is a missing
$ sign in mov _stack, %esp. Thanks to Ronald G Minnich for
catching that bug.

The second bug is the 'incl %eax', which shouldn't be there, as
there's no secondary CPU with index 0. CPU0 uses always the stack
below _estack.

Change-Id: Id267a654ba95b0e898eeaaafb2403b438250a563
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1212
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-07-12 07:11:57 +02:00
Kyösti Mälkki bc8c996608 Fix APIC cpu_index
If a CPU was pre-allocated, cpu_path is not copied and thus
index would not be updated. This breaks cpu_index() and AMD
model_fxx is possibly broken without this patch.

Change-Id: I77483181cf0bca31423c655942c022bffab3c7ea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1199
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-10 19:53:43 +02:00
Kyösti Mälkki a5650a4b4a Use dev_lock for alloc_find_dev()
If threads called alloc_find_dev() with same device_path
simultaneously, two device nodes could be allocated.
This bug is not triggered by current code.

Change-Id: Ifc87021c8d6f422901c5de5dd17392e3e2309afa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1188
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-10 19:52:24 +02:00
Kyösti Mälkki da09be6328 Drop start_cpu_lock
Function alloc_find_dev() is serialized.

Change-Id: I40d27d1adca629f1f7ce2f09c1cb2fd04b76eb9a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1198
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-10 19:51:47 +02:00
Anton Kochkov 54c07a675b msrtool: Add Intel Nehalem CPUs support
Added Intel processors based on Nehalem
architecture support, with decoding MSRs.

Change-Id: I576d5eac2542c0b62852bf05e42bc98b134c7eae
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-10 00:57:35 +02:00
Anton Kochkov ffbbecc9ee msrtool: Fix Intel CPUs detection
Added vendor check in sys.c file and fixed models checking
in intel targets files.

Change-Id: I1ce52bbce431dea79e903d6bc7a12e5b9ad061be
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1169
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-10 00:56:49 +02:00
Raymond Danks e1e6a91ce0 mkelfimage: pkgdata directory created but never used
Remove superfluous pkg* definitions and installation of a target
directory directory that is never used.

Change-Id: I2addf3f316230cdd428def5889fd3beb7c40f422
Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
Reviewed-on: http://review.coreboot.org/1195
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-09 22:18:37 +02:00
Sven Schnelle 356a600907 servengines/pilot superio: add attribute unused
Not all users use both functions, so add __attribute__((unused))
to prevent compiler errors.

Change-Id: I8485bb9150b04d1f9fdc231152a43bcd6fc713a7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1193
Tested-by: build bot (Jenkins)
2012-07-09 12:36:02 +02:00
Sven Schnelle 6d03876aff SMBIOS: Add Type 38 (IPMI) data structure
Change-Id: I9b9a1c7b1cc4aaba7a4791f898653b6fe41d4fcb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1192
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-07-09 11:51:30 +02:00
Sven Schnelle 34d86f0c61 i5000: reset system if raminit fails
Don't stop if RAM init fails at first try. It's better to restart
and try again instead of failing on the first try if the second
try would have worked.

Change-Id: Ib5660265d5b10a01588f2e4022dac2ee34f2c6d0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1191
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-07-09 11:34:37 +02:00
Sven Schnelle 7435baa5c5 Add basic ipmi support
Implements support code for talking to IPMI hardware that uses
a KCS style interface.

Change-Id: I9895cc1bf29676115b167081b63b8a430e23eee5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1190
Tested-by: build bot (Jenkins)
2012-07-09 10:41:05 +02:00
Ricardo Martins f5062437dc IEI PM-LX-800-R11: Removed bogus Kconfig option
The Kconfig file for this board contains a bogus option called
CORE_GLIU, this change removes it.

Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1
Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
Reviewed-on: http://review.coreboot.org/1179
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-07-07 11:47:34 +02:00
Sven Schnelle 56dfc7c684 inteltool: fixup intel 5000 chipset pci ids
Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1175
Tested-by: build bot (Jenkins)
2012-07-06 16:40:46 +02:00
Sven Schnelle 7b48379575 i5000: Add PCI ids for all i5000 flavours
Change-Id: I48be647e3f38038830200bcc64429cbf86990ad7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1174
Tested-by: build bot (Jenkins)
2012-07-06 16:40:30 +02:00
Ricardo Martins 0ca02553e1 IEI PM-LX-800-R11: Added preliminary mainboard support
Details for this board are available at
http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110

Most of the functionality provided by the original BIOS is
implemented.

Change-Id: Id9eb10a2f9e49377ea587bddadbba7d76223a715
Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
Reviewed-on: http://review.coreboot.org/1168
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-06 14:26:38 +02:00