This patch includes (edk2/edk2-stable202111) all required
headers for edk2-stable202111 EDK2 tag from EDK2 github
project using below command:
>> git clone -b edk2-stable202111 https://github.com/tianocore/edk2.git
commit hash: bb1bba3d776733c41dbfa2d1dc0fe234819a79f2
Only include necessary header files.
MdePkg/Include/Base.h was updated to avoid compilation errors
through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.
Note: edk2-stable202111 tag is required to adopt FSP 2.3 specification.
- Need to add ExtendedImageRevision in FSP_INFO_HEADER structure.
- Need to add FSP_NON_VOLATILE_STORAGE_HOB2 header.
Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
coreboot code currently supports different UDK binding as per
underlying FSP requirement, example: ICL and TGL uses
UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig.
These UDK binding Kconfigs are being used to choose the correct
UDK_VERSION.
This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION
if clause don't need to add specific UDK binding Kconfig everytime with
introduction of newer UDK bindings in future.
Tested with BUILD_TIMELESS=1, Hatch remains identical.
Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fix the issue that power consumption of single rank DRAM is greater
than dual rank DRAM due to incorrect settings of rank1 CKE.
Set rank1 CKE to the correct state to fix this issue.
BUG=b:196867407
TEST=DUT can boot to OS.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If336197aea4770dda1332b6e83da8ec9a4f9d77b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to
google internal repo. The dismatched size of HOB causes the wrong data
tranfer. So the coreboot also need to change.
BUG=b:204732649
Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove unused code and comment to align with the latest MTK memory
reference code which is from MTK internal dram driver code without
upstream.
version: Ib59134533ced8de09d23dd9f347c934d315166e2
TEST=boot to kernel
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as
specified in the DXIO descriptors. This change requires FSP version
1.0.4 revision 2 otherwise setting this value does affect any FSP
behavior.
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Remove unused drivers and some fast calibration implementations
to align with the latest MTK memory reference code.
TEST=boot to kernel
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2374_01.
Previous FSP version was v2347_00.
Changes Include:
- Offset change in FspmUpd.h and FspsUpd.h
BUG=b:201239436
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4150766
Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.
BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.
Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Some headers in vendorcode are still needed but the UPD definitions
can be taken from the FSP repo.
Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot expects different names for FSP UPDs so use some CPP to make
it happy.
Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix the two issues below.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18
ubsan: unrecoverable error.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18
ubsan: unrecoverable error.
Found by: UBSAN
Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The Kconfig options for custom SPD values aren't supposed to be part of
the choice block.
Change-Id: I12eb1012f94000b14e5d7f1e5123dddf69ac1a94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57717
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DSM methods as per the connectivity document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:191720858
TEST=Check the generated SSDT tables for DSM methods
Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for the WTAS ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the WTAS related configuration values and
verified that the SSDT has the WTAS ACPI table.
Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for the PPAG ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the PPAG related configuration values and
verified that the SSDT has the PPAG ACPI table.
Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support for intel wifi 6 and wifi 6e
configurations as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration block sizes were static in the
legacy SAR file format. Following is the format of the new binary file.
+------------------------------------------------------------+
| Field | Size | Description |
+------------------------------------------------------------+
| Marker | 4 bytes | "$SAR" |
+------------------------------------------------------------+
| Version | 1 byte | Current version = 1 |
+------------------------------------------------------------+
| SAR table | 2 bytes | Offset of SAR table from start of |
| offset | | the header |
+------------------------------------------------------------+
| WGDS | 2 bytes | Offset of WGDS table from start of |
| offset | | the header |
+------------------------------------------------------------+
| Data | n bytes | Data for the different tables |
+------------------------------------------------------------+
This change supports both the legacy and the new format of SAR file
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different
binaries generated by setting different versions in the config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
IDS (Integrated Debug Services) options are meant to be enabled when one
wants to debug AGESA. Since they are compile-time options, using Kconfig
is the logical choice. Currently, none of the options builds.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and Asus A88XM-E does not change.
Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The `ASSERT` macro is already defined in `src/include/assert.h`, and
AGESA's definition is never used. On Asus A88XM-E, toggling the value of
the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary
when using reproducible builds. Attempting to use AGESA's definition of
the `ASSERT` macro results in build errors:
In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info':
src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value]
#define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
Given that coreboot's definition of `ASSERT` is more useful, drop
AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro.
Also remove the `IdsAssert` function, as it is no longer used anywhere.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Disable reading of vdram/vddq/vmddr to reduce access of I2C
to reduce DRAM init time by about 30ms.
The values were only needed by HQA report and not needed on
production units.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I32cd68fb8b52cec6e145d6772475fde0130ca6ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56850
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support the config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT to limit DRAM
frequency counts to reduce DRAM initialization time by about 100ms.
BUG=b:195274787
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ibcb9a50c24f428358ef682b64946d4c91ebd81d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This symbol is only used in generating a default fmap.
Change-Id: I8d92eba9978cdad5795b0f5755e1d75db7b3cb2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The headers added are generated as per FSP v2237_00.
Previous FSP version was v2207_01.
Changes Include:
- Add VccInAuxImonIccImax in FspsUpd.h
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:192199787
BRANCH=None
TEST=Build and boot brya
Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c
Cq-Depend:chrome-internal:3970327,chrome-internal:3925290
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the implementation for vcore voltage control.
Also remove the reporting of vio18 because it is fixed during DRAM init,
and we won't provide drivers for reading or writing it.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FirmwareVersionInfoHob.h is removed in JSL FSP v2376 so
remove it from Jasper Lake vendorcode.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: Iad0429630665f50dbc1541487c9061dd1a19907c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45908
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update MdePkg/Include/IndustryStandard/SmBios.h to avoid compilation
errors through safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2
Kconfig.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patches in relation chain
and verify the version output prints no junk data observed.
Couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I9698861be1f969ddca7f171767a54ac486502c74
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45906
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support DRAM HQA HV/LV test, add an interface for adjusting the DRAM
voltage in DRAM fast calibration flow.
Normal boot flow will not be affected.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I4dbb4cb546e6e60693743ffe26b0df28ea501618
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55752
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Subrata Banik