Enable Image Processing Unit and CIO2 device that constitute IPU3.
BUG=None
TEST=Build and boot up into Nocturne platform and check with lspci.
Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/27124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sensors and CSI2 receiver configuration for Nocturne platform.
IMX355 module has VCM, NVM and is on the second port of receiver.
IMX319 module has NVM and is on the first port of receiver.
Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/26283
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These bits start the acquisition process. They should only be set by the
driver.
BUG=b:74363445
TEST=compile
Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/27265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to sona thermal table, PL2 need to check cpu id.
And then set PL2 value.
BUG=b:110867809
TEST=The thermal team verify OK
Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit changes the uid and desc fields for the sx9310 entries
in the devicetree to be unique, and correctly identify the position
of the respective sensors.
Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
We would use GPP_B20 instead of board id to determine nautilus SKU.
BUG=b:80052672
BRANCH=poppy
TEST=Verified the new coreboot could determine SKU correctly
Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27220
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V
leakage. To fix this problem, add GPP_C3 into config for Pantheon
Synaptics touchscreen.
BUG=b:78436458
BRANCH=None
TEST=Let DUT in S0ix mode and check GPP_C3 is normal.
Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures a GPIO pin for enabling/disabling bluetooth on the
next version of the atlas board. The default is for bluetooth to be
enabled at this point.
BUG=b:110614620,b:110613353
BRANCH=none
TEST=none
Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.
This patch fixes the above issue.
BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.
Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a temporary hack to test camera presence before we have full
camera support implemented. Basically, we can now probe the camera
over i2c to verify that it's connected and the camera LED turns on.
BUG=b:80106316
BRANCH=none
TEST=camera LED comes on and camera can be probed over i2c.
Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27128
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We plan to use i2c-hid compatible trackpads on atlas, so this switches
the trackpad config to i2c-hid.
BUG=b:80662079
BRANCH=none
TEST=used trackpad to verify motion tracking
Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27126
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change defines SAR sensor device into devicetree.cb.
Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio.
BUG=None
BRANCH=poppy
TEST=Verified SAR sensor device is loaded by driver in Chrome OS
Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27149
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.
BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot
Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.
BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update dptf.asl and TCC parameters from tuning of the thermal team.
BUG=b:72974136
TEST=Match the result from DPTF UI
Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an
output and initialize it high (high = out of reset).
BUG=b:80089559
BRANCH=none
TEST=none
Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of
GPP_D8 as it needs a 3.3v gpio to provide enough power to also
directly power the camera LED.
BUG=b:79667559,b:78122599
BRANCH=none
TEST=none
Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Add tablet motion control config to nami devices.
BUG=None
BRANCH=None
TEST=run evtest
make sure tablet switch value is 1 in tablet mode and 0
when not in tablet mode
Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26970
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TPM over SPI/I2C config selection got changed in
https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the
same.
BUG=None
BRANCH=None
TEST=Build for Soraka & make sure that TPM is probed over I2C interface
rather than SPI.
Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26890
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since there are two cameras on Nami and only one camera on Pantheon.
We need to disable rear camera/DMIC on all Pantheon sku.
BUG=b:109720689
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Pantheon
Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Issue observed on the board is: too many jack interrupts.
cat /proc/interrupts | grep da7219
58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad
Updated pad configuration for Jack IRQ pin to fix the issue.
BUG=b:109655907
TEST=Jack insertion & removal detection is working.
Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
During measurement of signals during Elan touchscreen power on, saw
that the enable_gpio delay was not sufficient as there is a +1.5 ms
delay during power on. Adding more delay to take this into account.
BUG=b:78311818
BRANCH=None
TEST=probe power on signals to ensure meet timing requirements
Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Power off does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/power off.
BUG=b:78311818
BRANCH=None
TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled
Make sure delays are consistent with spec
Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Vayne added one more skuid 3A67, we need to disable rear
camera/DMIC for vayne skuid 3A67.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Vayne
Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26855
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The driver only supports streaming images flipped horizontally
and vertically. In order to ensure that all current users will
be fine if or when support for upright streaming is added,
require the presence of the "rotation" control now.
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792
Signed-off-by: Lai, Jim <jim.lai@intel.com>
Reviewed-on: https://review.coreboot.org/26727
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves PL2 override to variant_devtree_update for two reasons:
1. This function was added to basically override devtree settings in
variant specific code. So, it would be a good idea to perform all the
overrides in a single place.
2. Adding a device for performing nami_enable would require changes to
devicetree and special handling for calling this device enable. Thus,
nami_enable was never getting called.
BUG=b:80148703
Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"
Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
