Commit Graph

49717 Commits

Author SHA1 Message Date
Bo-Chen Chen 511884e7e8 soc/mediatek/mt8188: Rename SPM register
The SPM register at offset 0x0 is often named as poweron_config_set in
previous MediaTek SoCs. To use common driver, we rename it from
poweron_config_en to poweron_config_set.

BUG=none
TEST=emerge-geralt coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:28:11 +00:00
Rex-BC Chen d641addf38 soc/mediatek: Add support for input 1P mode of dp_intf
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct
member `input_mode` is added to `struct mtk_dpintf` for
differentiation. We also move SoC-specific data `dpintf_data` to soc
folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25 08:27:52 +00:00
Bo-Chen Chen 319fce53c8 soc/mediatek: Move DP drivers to common
DP drivers can be shared for both MT8195 and MT8188, so move them to
common folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:27:31 +00:00
Elyes Haouas 193e86b814 mb/clevo/tgl-u: Avoid indirect includes
Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-10-24 20:04:15 +00:00
Felix Held 2a09a84f15 mb/google/kahlee: always detect ELAN touchpad
Always detecting the presence of the ELAN touchpad doesn't affect the
functionality, but allows dropping the override for all variants that
have multiple touchpad options.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-24 15:50:46 +00:00
Felix Held 34362d0c0f mb/google/kahlee: use override devicetrees for variants
This helps with deduplicating the identical parts of the variants'
devicetrees.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-24 15:50:39 +00:00
Martin Roth fed17f968d MAINTAINERS: Add Matt DeVillier to the release team
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6f5c10618edb87d2dc12c14187c4620d8675a443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-24 13:02:39 +00:00
Elyes Haouas 53e3c2414d Update arm-trusted-firmware submodule to upstream master
Updating from commit id c45d2febb:
2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration)

to commit id 61fe7826d:
2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration)

This brings in 10 new commits:
61fe7826d Merge "feat(fvp): build delegated attestation in BL31" into integration
cf17f7c45 Merge "chore(rpi3): remove redundant code" into integration
70360382b Merge "docs(maintainers): add NPU driver owners" into integration
60c439435 docs(maintainers): add NPU driver owners
e504ce5fa Merge "fix(versal_net): Enable a78 errata workarounds" into integration
bcc6e4a02 fix(versal_net): Enable a78 errata workarounds
0271eddb0 feat(fvp): build delegated attestation in BL31
6047ab122 Merge "fix(versal): enable a72 erratum 859971 and 1319367" into integration
769446a68 fix(versal): enable a72 erratum 859971 and 1319367
2594759d2 chore(rpi3): remove redundant code

Change-Id: Ic32c0889961f529e1762b208ef118a94369c34e6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-24 13:01:48 +00:00
Patrick Rudolph e249b1a313 arch/x86: x86_64 implies SSE2 support
Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume
SSE2 is present and enabled when targeting x86_64.

This fixes:
- lzma decompression code is compiled with the -Ofast flag
- 'everything' when compiling with clang.

This mostly affects qemu targets, which did not have this flag selected
yet.

TESTED on qemu.

Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-24 12:16:32 +00:00
Sam McNally 1347571f9b mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBER
For some nissa variants, there are build configurations that need to use
different blobs, but otherwise are identical. Currently, they use the
same choice of board config and configure blob paths appropriately. This
avoids duplication within the Kconfig file, but the resulting firmware
images can be difficult to distinguish, since they report the same
FRID.

Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden
and round-tripped through make oldconfig, allowing customisation of the
reported FRID and other MAINBOARD_PART_NUMBER-derived values with
minimal overhead.

BUG=b:253966060
BRANCH=None
TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully

Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-24 11:58:49 +00:00
Michał Żygowski b205c5d8c1 util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo
Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the
patch adding register definitions for NCT6687D Super I/O chip.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-24 09:08:40 +00:00
Martin Roth 94008a81e5 soc/amd/mendocino: Add STB Spill-to-DRAM enum
This is the enum value to initialize the Smart Trace Buffer's
Spill-to-DRAM feature.  More information on how this is used is
available in the STB Linux kernel driver.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-23 14:40:51 +00:00
Elyes Haouas 1e336dd91e scripts/update_submodules: Fix "bad revision" error
Fix "bad revision" error when we run "update_submodules" with no option.
This adds "origin/trunk" branch name for "util/goswid".

Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-23 02:39:27 +00:00
Martin Roth 08e7df9d5d configs: Add skyrim config with binaries
We've seen failures because the binaries were not being built into the
image.  In particular, the APCB is modified by the coreboot build
process, so if the APCB isn't built correctly to support the correct
number of SPDs, the build can fail.

The mendocino FSP binaries are not yet pushed, so the build is currently
pointing at the cezanne binaries.  The mendocino FSP will be pushed when
the mendocino chips are released for sale.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I31d11c5327416f4339930373c447531ae9f79d28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-22 22:44:09 +00:00
Fred Reitberger c6d7fca0cc soc/amd/morgana/mca: Update for morgana
Update the MCA bank names for morgana per PPR #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22 22:30:09 +00:00
David Wu 44cc1b9cac mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W
based on fw_config.

BUG=b:253542746
TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22 22:28:32 +00:00
Derek Huang 3d2df35c6e mb/google/brya: Enable SaGv for brask variants
SaGv is enabled for all brya variants, so it should be harmless
to enable it for brask variants to save some power.

BUG=254374912
TEST=Build and boot to Chrome OS

Signed-off-by: Derek Huang <derekhuang@google.com>
Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22 22:27:51 +00:00
Frank Wu c9043411b3 mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ
The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects.
Therefore, update the gpio.c to be consistent with the configuration.

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-22 17:12:32 +00:00
Sean Rhodes 7bbc9a512a payloads/edk2: Disable the CPU Timer Lib unless supported
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp
Counter Frequence. For CPUs that do not support this instruction, EDK2
must include a different library which is the reason why this must be
configured at build time.

If this is enabled, and the CPU doesn't support 0x15, it will fail to
boot. If is not enabled, and the CPU does support 0x15, it will still
boot but without support for the leaf. Consequently, disabled it by
default.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22 17:11:25 +00:00
Sean Rhodes 27c8bf0cc9 payloads/edk2: Add the recipes to assemble UniversalPayload
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id6363c92f8155007e05c682694d7413fd4630b6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22 16:48:00 +00:00
Arthur Heymans c37fd87d85 soc/intel/systemagent: Rewrite using new resource API
Working with resources in KB is tedious and the base_k / size_k variable
naming was simply wrong in one case.

Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 16:46:40 +00:00
Arthur Heymans 9c2f3cc9d9 soc/intel/systemagent.c: Fix memory type reporting
TOLUD stands for top of lower usable dram. Memory between cbmem_top and
TOLUD, even if stolen for another device/purpose can still be marked WB
cacheable. This will result in a cleaner MTRR setup.

Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22 16:45:29 +00:00
Werner Zeh 6537216b7a mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2
variants in order to provide the real delay value for the VCC supply
rail. This delay is needed to enable proper switching between different
VCC levels based on current system state.

Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 16:42:22 +00:00
Matei Dibu 516eff01e6 arch/x86/include/arch: fix assembly clobber for 64bit
the "x86 PIC code ebx" workaround done previously
by commit 689e31d18b ("Make cpuid functions usable
when compiled with PIC") does not work for x86_64
(the upper dword of rbx is set to 0)

the GCC bug that needed the workaround was fixed
in version 5 (see GCC bug 54232)

Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95
Signed-off-by: Matei Dibu <matdibu@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-22 16:40:42 +00:00
Angel Pons 436f1c471a mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.

However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.

For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.

BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().

Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 16:39:05 +00:00
V Sowmya 036b16b884 soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control
Enable the VCCST ICCMax Control for the ADL-N display flicker issue.
Please refer the Doc with ID 742988 for more details.

BUG=b:248249033
TEST=Verified that the display flicker issue is fixed.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-10-22 16:36:02 +00:00
Elyes Haouas 901566597e nb/intel/i945/raminit: Use 'bool' for do_reset
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 05:14:35 +00:00
Elyes Haouas d9dade3cb9 nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 05:14:11 +00:00
Elyes Haouas 5bbdb0c948 smbios.h: Add High Bandwidth Memory Generation 3
Add HBM3 according to SMBIOS 3.6.0:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

Change-Id: Id8473e8c4b5006b53b5ff9de7825d15595f2a616
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 05:13:27 +00:00
Elyes Haouas 26fc2a40ae nb/intel/i945/raminit: Use 'size_t' for banksize[]
Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 05:12:22 +00:00
Martin Roth f690c93f25 vc/amd/fsp: Get rid of last "sabrina" reference
We still had a lingering reference to the old sabrina codename in the
vendorcode directory.  Searching through the code now, the only places
the sabrina codename is seen is in the release notes, as is proper.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 01:59:17 +00:00
Fred Reitberger 81b5631258 soc/amd/*/i2c.h: Make definition more accurate
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL
definitions instead of BIT(x).

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22 01:59:00 +00:00
Reka Norman ec929142c6 mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
On nissa, the pre-x86 time is not part of the 1s firmware boot time
target. Including the pre-x86 timestamps causes confusion since the boot
time appears to be greater than 1s, so disable the Kconfig on nissa.
We're not doing any analysis or optimisation of the pre-x86 time on
nissa anyway, this work will start from MTL onwards. Also, the Kconfig
is already disabled on the brya firmware branch, so this will result in
the same behaviour as brya.

Before:
Total Time: 1,205,840

After:
Total Time: 995,300

BUG=b:239769532
TEST=Boot nivviks, check "1st timestamp" is the first timestamp.

Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 01:53:57 +00:00
Elyes Haouas 73fec24319 mb/lenovo/*/mainboard.c: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-22 01:53:36 +00:00
Matt DeVillier f0f73bdb1d mb/google/kahlee: Fix audio ACPI inclusion
Not all kahlee variants use the RT5682 audio codec, so split the
baseboard audio ACPI into two parts and only include the asl for
the codec(s) actually needed for a given variant.

TEST=build/boot aleena, liara variants and verify no ACPI present
for RT5682 codec (which is not present on the boards).

Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22 01:53:11 +00:00
Shaik Shahina 16ae1cf233 vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04.

Changes include:
- FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD

BUG=b:254374913
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.

Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424
Reviewed-by: Reka Norman <rekanorman@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 01:52:35 +00:00
Frank Wu b56a8d0272 mb/google/skyrim: Enable genesyslogic gl9755 for frostflow
Enable DRIVERS_GENESYSLOGIC_GL9755 support for frostflow

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1db598c68687ed17fd9baa3567ab8fdd3e4fb6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-21 22:06:35 +00:00
Fred Reitberger 460ea9d5d2 soc/amd/*/smi.h: Use BIT() for clarity
Use the BIT() macro for single-bit constants.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I490f0093d55813260fcdb7303a94accfa90e75e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-21 21:42:00 +00:00
Arthur Heymans 1cffc55d35 util/amdfwutil: Fix adding microcode binaries
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 21:40:08 +00:00
Felix Held 3adfeec58f soc/amd/*/uart: cleanup includes
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-21 21:03:33 +00:00
Angel Pons 669a767635 mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2
Built from a mixture of autoport output, other variants, schematics and
expert guesswork. I don't have this board, but the code has been tested
by someone else and boots successfully (first try) with TianoCore. It's
reasonable to assume most things work, as this board is very similar to
the already-supported variants.

Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 19:05:40 +00:00
Martin Roth 66f1a98e7f arch/x86/include: Split msr access into separate file
To allow testing of code that uses msr calls, separate the actual
calls into a separate header file,  This allows the tests to emulate
the msr access without replacing the rest of the msr.h definitions.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I102709fec346f18040baf9f2ce6e6d7eb094682d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 15:01:00 +00:00
Sean Rhodes 88058a26f0 MAINTAINERS: Remove Andrey Petrov from Apollo Lake
Andrey doesn't seem to have interacted with APL or coreboot
2+ years, so remove him and mark Apollo Lake as orphaned.

Add myself for Odd Fixes.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6cb2f2da63dda3cb841786d53f89b583a9df9791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:57:53 +00:00
Elyes Haouas d0a5688a93 mb/lenovo/t{410,60}/dock.h: Fix header guards
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7b279cf2c69f62b47ef497edd372034f148fff03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:57:32 +00:00
Rex-BC Chen a6cd1bd6a8 soc/mediatek: Unify PLL function names
For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().

BUG=none
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:57:09 +00:00
Sen Chu 08248c0ce8 mb/google/corsola: Initialize MT6315 for MT8186T
Initialize MT6315 for powering on big cores on MT8186T.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68621
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:56:44 +00:00
Sen Chu 122b45be6e soc/mediatek/mt8186: Add support for PMIC MT6315
On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:56:32 +00:00
Sen Chu 28dceaec71 soc/mediatek: Move SPMI interface configuration to SoC folder
The SPMI interface configuration is SoC-dependent.
- MT8192 and MT8195 are the same.
- MT8186 does not need to implement this.
- MT8188 is different from MT8195, and we will submit another patch to
  fix this.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:53:53 +00:00
Rex-BC Chen 1543252e5f soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig option
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't
need to configure PMIF SPMI IO pins. Add a config to control that.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:53:02 +00:00
Rex-BC Chen 6d449e005c soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig option
On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other
MediaTek SoCs support PMIF_SPMI and PMIF_SPI.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:52:42 +00:00