Commit Graph

35844 Commits

Author SHA1 Message Date
Angel Pons f67bf49ead nb/intel/i945: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: Ibf6904246ee47dffdb5fa2e24cc7a230f439c7e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43178
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:08:37 +00:00
Angel Pons 837141fa56 nb/intel/i945/acpi: Tidy up comments and cosmetics
Use C-style comments, drop unneeded newlines, add missing commas for
consistency and relocate a comment to match the code.

Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:08:27 +00:00
Angel Pons 29cd350c46 nb/intel/gm45: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Ibb9b627de85eb09bdc977af55880366e4e49f3ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08 22:07:38 +00:00
Angel Pons d85d7e2329 nb/intel/gm45: Tidy up comments and cosmetics
Use C-style comments, drop an unneeded newline, add missing commas for
consistency and relocate a comment to match the code.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:07:27 +00:00
Angel Pons 7c71f7d15b nb/intel/x4x/acpi: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I089f14dce6e3fdebcfdee126a2023ef028a01805
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08 22:07:10 +00:00
Angel Pons 0b5673dd33 nb/intel/x4x/acpi: Clean up comments
Use C-style comments. Also drop some unnecessary newlines.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: Icd33a326cc7d9ead765e2b32e7dea237bd76fd4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-08 22:06:48 +00:00
Martin Roth 6e5f909830 soc/amd/picasso: Update APOB size & base generation
Make the APOB size & base generation the same as all the other command
line arguments to amdfwtool.

BUG=None
TEST=Build & boot trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id78383d87bc98dd2c859c75585266411c226f950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 21:07:00 +00:00
Martin Roth 00b37d3007 arch/x86: Add memmove.c to x86 bootblock
This was specifically needed for vboot with psp_verstage, but adding
it to always be built into bootblock if needed like memcpy & memset
makes sense.

TEST=Build & boot trembyle
BUG=None

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 21:06:47 +00:00
Martin Roth c35d4fa377 mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 21:06:34 +00:00
Martin Roth f38af663d2 src/amd/common: Exclude biosram from psp_verstage
This isn't needed for psp_verstage, and causes build failures if
included.

BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I63942ad896d205c327d65bb8083da817b972962b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42808
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 21:02:31 +00:00
Martin Roth 95d05e43b1 soc/amd/picasso: Halt if workbuf is absent after psp_verstage
Check for the workbuf in bootblock if psp_verstage is being used.

BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 20:46:05 +00:00
Martin Roth 137f86149e soc/amd/common: Don't init SMIs or SCIs in psp_verstage
We can't set the SMI or SCI flags in psp verstage, so skip them.

TEST=Build
BUG=b:154142138

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 20:42:07 +00:00
Martin Roth d09b9747e7 lib: Temporarily remove timestamps from psp_verstage
The timestamp functionality is not yet added for psp_verstage, so
temporarily remove it until that's completed.  That work is being
tracked by bug 154142138.

BUG=b:154142138
TEST=Build & Boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I020619e3615ce92dedbe868104d2bfd83cb7caa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 19:37:50 +00:00
Martin Roth 9aa8d11885 soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings.  When these are moved to the RW-A & RW-B
regions, the packages need to be recreated for the new addresses.

TEST=Build & boot trembyle. See that we're booting from the correct
region.
BUG=b:158124527

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 19:37:11 +00:00
Martin Roth 6303671189 security/vboot: Allow files to go into only RW-A or RW-B region
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings.  This means that we need different copies
of the package in each region.
This change allows for the different files in each of the 3 vboot
regions.

BUG=b:158124527
TEST=Build trembyle; see the correct versions of the files getting
built into the RW-A & RW-B regions.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45ff69dbc2266a67e05597bbe721fbf95cf41777
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 19:36:24 +00:00
Martin Roth 362eaf3f4c soc/amd/picasso:Add psp_verstage components to amdfw binary
This adds the psp_verstage userspace application and the location of
the shared memory area to the amdfw binary tables.

BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
2020-07-08 19:35:27 +00:00
Martin Roth c7acf1666a soc/amd/picasso: add psp_verstage
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP.  It does a minimal setup of hardware,
then runs verstage_main.  It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.

BUG=b:158124527
TEST=Build & boot trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 19:34:59 +00:00
Martin Roth ac41f58235 soc/amd/picasso: Allow modification of i2c base addresses in PSP
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42064
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 19:34:44 +00:00
Maulik V Vaghela ab70d0ff66 mb/google/waddledee: Enable Audio
1. Enable HDA Pci device in devicetree
2. Enable I2C4 in devicetree and fill ACPI information
3. Pass correct IRQ GPIO for headset jack

BUG=None
BRANCH=None
TEST=Audio playback and recording works on Waddledee.

Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41765
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 18:46:39 +00:00
Patrick Georgi b351875f1e build system: Rely on xcompile for HOSTCC and HOSTCXX
It already looks for them, so let's use the result instead
of blindly defaulting to gcc/g++, except when not building an image
(but run kconfig or tests) because we don't use xcompile in those cases.

Change-Id: I3e50c70a609f1903a925610928f8779c191040d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-08 08:53:46 +00:00
Patrick Georgi 793bf7e605 util/xcompile: Look for the host compiler in XGCCPATH, too (and first)
If there's a host compiler in XGCCPATH, it's likely the same
relatively-current version we use for coreboot, and it's a well-known
quantity, so let's prefer that over alternatives by default.

In addition, look for the C++ host compiler as well.

Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 08:53:41 +00:00
Kyösti Mälkki fca0cba6a1 sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
The smm_setup_structures() calls placed GNVS address into
register %ebx. Old code on i82801dx used these low memory
addresses.

Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:33:00 +00:00
Kyösti Mälkki e769bcee9a ACPI: Add and fill gnvs_ptr for smm_runtime
Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-08 07:32:51 +00:00
Bryant Ou da1fde2ffb mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
BIC uses LPCflash utility to flash FW, it uses LPC to send the
bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used
to send BIC image for in-band update support.

TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.

[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin
Update Bridge IC Firmware from LPC

Deltalake linux utility ver:1.01
build time: Feb 11 2020 14:30:55
Processing image file: Y3BRDL_D06.bin
.. of size 206968 (0x00032878) bytes
.. file will be padded to a 64-byte size
.. with DEBUG Enabled
Generating CRC-32 for file.
Done (0x4e3905a3).

iBytesRead (0x00007c00).

Discovering LPC boot loader.
Discovered @ 0x3f8.

Configuring LPC boot loader.
Configured @ 0x00000600.

Sending header block.
Sent.

Loading firmware into target.
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 16512 bytes .................
Load complete.

Update done!

Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08 07:31:08 +00:00
Wisley Chen 742bccfb5c mb/google/dedede/var/drawcia: add elan touchscreen
BUG=b:155002684
TEST=build drawcia, and check touchscreen can work

Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-08 07:30:07 +00:00
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00
Patrick Rudolph d5321bf2fb Documentation: Add TODOs for secure SMM when using x86_64
Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 07:27:52 +00:00
Angel Pons 9d69d881e6 nb/intel/haswell/acpi: Update to ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43152
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:26:25 +00:00
Angel Pons 05f996d433 nb/intel/haswell/acpi: Fix host bridge registers
The host bridge register definitions haven't changed from Sandy Bridge
to Haswell, according to the datasheets. However, coreboot's ACPI code
is not the same. Looks like Haswell values are wrong, so correct them.

Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-08 07:26:07 +00:00
Michael Walle 32b13131c1 libpayload: arm64: silence libpayload main entry
No other architecture in libpayload outputs anything in the main entry
routine. Let alone an exception test which looks like a real exception
to the normal user and is most likely really misleading. Silence the
startup code.

Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43126
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:25:38 +00:00
Michael Walle 492d55fa46 libpayload: arm64: fix OUTPUT_ARCH()
There is no bfd "arm64". The correct bfdname is "aarch64". Fix it. With
this change libpayload will build with the AArch64 GCC.

Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-08 07:25:03 +00:00
Johnny Lin 3d44c9925f mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in romstage
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value. By default it would start the timer and
trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.

Tested on OCP Delta Lake.

Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08 07:24:22 +00:00
Johnny Lin cef108cc90 mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs
In romstage get the config from BMC IPMI and update the IIO accordingly.

Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation
register values are expected.

Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-08 07:24:11 +00:00
Wisley Chen b8fbf3f972 mb/google/dedede/var/drawcia: Support Elan touchpad
BUG=b:155002811
TEST=build drawcia, and check touchpad can work.

Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42922
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 03:49:40 +00:00
Julius Werner 984a6b43d4 google/trogdor: Add new variant Pompom
This patch adds a new variant called Pompom that is identical to Lazor
for now. Also reorder variants alphabetically while we're here.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5a0f297413765bce8353d5a781f0f67446de4e7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-07-07 22:46:13 +00:00
Jonathan Zhang e4aab352ee vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.

The CPX-SP soc code is updated to direct FSP log to SOL.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 22:24:41 +00:00
Sam Lewis e69b1af925 armv7: mmu: Use 'tlbimva' to invalidate TLB entries
The tlbimvaa operation (invalidate unified TLB by MVA, all address
space identifiers) is only available on armv7 processors that support
Multiprocessing Extensions. When used on processors that do not support
the extensions it causes an "undefined instruction" exception.

This patch changes the MMU table entry filling code to use the tlbimva
(invalidate unified TLB entry by MVA and address space identifier)
operation for invalidating TLB entries, which is supported on all armv7
processors.

As address space identifiers are not used in TLB entries in coreboot
(all entries are set as global), these two operations can safely be
used interchangeably. The ASID value supplied to the operation is not
checked for global TLB entries.

More information as well as the data formats for the tlbimvaa and
tlbimva operations are detailed in the "ARM Architecture Reference
Manual ARMv7-A" edition, issue "C.c" page B4-1747.

TEST: Booted Beaglebone Black (my current in progress port)

Change-Id: Ie7dfb4adab20dc7eecb1b20aa2ee6355215a1521
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-07 21:48:30 +00:00
Tim Wawrzynczak 93d7bcbc67 ec/google: Add function ec_fill_dptf_helpers()
ec_fill_dptf_helpers() is used to generate all of the "helper" methods
that DPTF requires. A system with a Chrome EC is typically in charge
of fan PWM control as well as battery charging, so if DPTF needs to
manipulate those, then it requires Methods provided by the EC.

BUG=b:143539650
TEST=compiles

Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41894
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 20:31:30 +00:00
Tim Wawrzynczak f694502697 acpigen: Add acpigen_notify
A fairly common thing in ACPI is notifying a device when some kind of
device-specific event happens; this function simplifies writing this
pattern.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42102
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 20:31:22 +00:00
Tim Wawrzynczak c5316ec4d6 soc/intel/common/block: Add new block DTT
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.

Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 20:31:14 +00:00
Nico Huber 3452cb1359 mb/lenovo/t60: Fix override devicetrees
When converting to override trees in commit c1dc2d5e68 (mb/lenovo/t60:
Switch to override tree), some device nodes were missed. These are
essential, as `chip` configuration data is always tied to device
nodes. The resulting `static.c` contained multiple copies of the
`chip` configuration structs, but the wrong ones were hooked up.

The therefore missing configuration of the clock gen led to general
instability, especially with SMP under Linux (probably due to the
attempt to enter lower C states on an idle core). Passing `maxcpus=1`
to the Linux kernel served as a workaround.

Change-Id: I6c26d633d1860cf9a5415994444e75ae1c2e59ad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43150
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 19:30:47 +00:00
John Zhao 5d16a25e0c soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master
This change disables Thunderbolt PCIe root ports bus master before
handing over to payload in order to mitigate the threat from the
unauthorized external DMA. In this state, the PCIe root ports would
be considered as trusted to not forward any DMA transactions to
downstream endpoint devices.

BUG=b:141609884
TEST=Verified PCIe resource has been allocated properly and USB behind
Thunderbolt dock is enumerated successfully.

Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-07 17:29:56 +00:00
Anna Karas cb01c2a315 src/include: improve the description of hexstrtobin
Specify how hexstrtobin.c processes the strings of odd length.

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ie8cd8fb93d7dab08c5e7f28fc511b6381f5ad13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43089
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:27:00 +00:00
Anna Karas 5664bc8cf9 tests: Add lib/hexstrtobin-test test case
Implement unit tests for lib/hexstrtobin module.

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Id929b07936ea180a798309e5acb1dacf1b396e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-07 17:26:42 +00:00
Peichao Wang c130687e1e mb/google/vilboz: Drop gpio.c from variants/vilboz
Update GPIOs since Vilboz hardware design
follow schematic V3.2, so gpio.c is unnecessary.

BUG=b:157744136
BRANCH=NONE
TEST=flash the bios to vilboz DUT and test touchpad function

Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42986
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:26:19 +00:00
Peichao Wang 1114b208a0 mb/google/vilboz: Fix variant ID for v3+ schematics for vilboz
At this moment, Vilboz board version is 1 and it
according to v3+ schematics, however WiFi power enable
is active high. This change sets
VARIANT_MIN_BOARD_ID_V3_SCHEMATICS for Vilboz as 1
and VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW as 2.

BUG=b:160547115
BRANCH=None
TEST=flash the bios to vilboz DUT and test WIFI module

Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-07 17:26:10 +00:00
John Zhao 7b46aae062 mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.

TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP
board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42953
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:26:08 +00:00
Daniel Kang 4db893b6fc mb/google/volteer: Change ov2740 HID of Chrome driver to match with
Windows definition

There was a review comment for Chromium Linux ov2740 driver that
Windows driver already set the HID as INT3474 and suggested to have
the same value for Chrome.

The upstreamed Linux driver code has INT3474 as HID and this patch is
to set the same HID in ACPI configuration.

https://patchwork.kernel.org/patch/11540753/

BUG=b:160334865
BRANCH=none
TEST=User-facing camera should work with the driver which set the HID
as INT3474

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43006
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:25:36 +00:00
Daniel Kang feb5d10061 mb/google/volteer: Fix world-facing camera LED is always on issue
Volteer world-facing camera has a privacy LED and it is supposed
to be turned on only when the camera is being used. But the LED
is always on and this is to fix the issue.
RCAM_SNR_PWR_EN (RearCAMera_SeNsoR_PoWeR_ENable) GPIO, which
controls the world-facing camera LED, was not in the power-up
and power-down sequence definitions and this caused the issue.

BUG=b:160341981
BRANCH=none
TEST=Build and boot volteer proto 2 board. Start a camera app
and check the world-facing camera LED is only turned on only when
the camera is working.

Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42985
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:25:25 +00:00
Tim Wawrzynczak 03465f4b0f dptf: Add support for IDSP
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the
implementation supports. Added a new acpigen function to figure out
which policies are used, and fills out IDSP appropriately.

Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:23:47 +00:00