Commit Graph

35844 Commits

Author SHA1 Message Date
Tim Wawrzynczak e4d8ebcef7 dptf: Add support for Fan and TSR options
DPTF has several options on how to control the fan (fine-grained speed
control, minimum speed change in percentage points, and whether or not
the DPTF device should notify the Fan if it detects low speed).
Individual TSRs can also set GTSH, which is the amount of hysteresis
inherent in the measurement, either from circuitry (if analog), or in
firmware (if digital).

BUG=b:143539650
TEST=compiles

Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:23:34 +00:00
Tim Wawrzynczak bb5c255907 dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes
the ranges available as knobs for DPTF to tune. It can support min/max
power, min/max time window for averaging, and the minimum adjustment size
(granularity or step size) of each power limit. The current implementation
only supports PL1 and PL2.

BUG=b:143539650
TEST=compiles

Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:23:16 +00:00
Tim Wawrzynczak 2ad8ffed6f dptf: Add support for Fan Performance States
This change adds support for generating the _FPS table for the DPTF Fan
object. The table describes different levels of fan activity that may be
applied to the system in order to actively cool it. The information
includes fan speed at a (rough) percentage level, fan speed in RPM,
potential noise level in centibels, and power in mA.

BUG=b:143539650
TEST=compiles

Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:23:01 +00:00
Tim Wawrzynczak 46f6fcf88f dptf: Add support for Charger Performance States
This change generates the DPTF TCHG.PPSS table in the SSDT. This table
describes different charging rates which are available to use. DPTF
can pick different rates in order to passively cool (or not) the
system.

BUG=b:143539650
TEST=compiles

Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:22:46 +00:00
Tim Wawrzynczak 3a9cde9ab6 dptf: Add support for Critical Policies
This patch adds support for DPTF Critical Policies, which are consist
of Method definitions only. They are `_CRT` and `_HOT`, which are
defined as temperature thresholds that, when exceeded, will execute a
graceful suspend or a graceful shutdown, respectively.

BUG=b:143539650
TEST=compiles

Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:21:07 +00:00
Tim Wawrzynczak 7eb1136c27 dptf: Add support for Passive Policies
This patch adds support for emitting the Thermal Relationship Table, as
well as _PSV Methods, which together form the basis for DPTF Passive
Policies.

BUG=b:143539650
TEST=compiles

Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:20:33 +00:00
Tim Wawrzynczak c41f7f15c1 dptf: Add support for generation of Active Policies
This change adds support for generating the different pieces of DPTF
Active Policies. This includes the Active Relationship Table, in
addition to _ACx methods.

BUG=b:143539650
TEST=compiles

Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:20:13 +00:00
Tim Wawrzynczak ff2f6b2478 drivers/intel/dptf: Add current participant Devices to DSDT
In this DPTF implementation, the participant device objects are written
into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID,
PTYP, and _STR). All other Methods & Names will be written into the
SSDT. If a device is not used in any policy, then its _STA is set to
return 0 ("off").

BUG=b:143539650
TEST=Compiles.

Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07 17:19:53 +00:00
Tim Wawrzynczak 4b748140ba soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_name
For both Tiger Lake and Jasper Lake, add the DEVFN for Image Processing
Unit (IPU) to soc_acpi_name, which is set to return "IPU0".

Change-Id: Ib11be5be7fbaec688d8788945a3bcab3f8d834a1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42878
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:07:11 +00:00
Tim Wawrzynczak c0199919e3 soc/intel/common: Add a minimal PCI driver for IPU
Add a minimal PCI driver for Intel's IPU, this allows devices to be
added underneath it in the devicetree.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I531b293634a5d40112dc6af7b33fedb5e13f35e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42812
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:07:01 +00:00
Tim Wawrzynczak c85d7c59ac pci_ids: Add TGL & JSL IPU PCI IDs
Add PCI IDs for Intel's Image Processing Unit (IPU) for TGL & JSL

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I71dc95a6692e82ca25b0252b4f0789ee059df89f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42811
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 17:06:52 +00:00
Patrick Georgi f2741aa632 util/crossgcc: Always bootstrap for gcc < 4.9
Building cbfstool requires at least 4.9 due to optimizer bugs in gcc
3.x to 4.8.x, so let's not work around ancient compilers in our tree
but ensure that users get a newer compiler.

Closes: https://ticket.coreboot.org/issues/240
Change-Id: I4e0f80e2790514e6a1b5d5de1a373f365df1569c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43143
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:45:40 +00:00
Sugnan Prabhu S b087a940a2 drivers/intel/mipi_camera: Add camera power resource to SSDT
This change adds support function to parse entries in the devicetree to
generate PowerResource entries for the MIPI camera.

Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41624
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:45:05 +00:00
Sugnan Prabhu S 4f77f61d2d acpi: add STA function to return external variable
This change adds support function to add STA function which returns an
external variable.

Change-Id: I31755a76ee985ee6059289ae194537d531270761
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42245
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:44:55 +00:00
Matt Delco 879b3c195f drivers/intel/mipi_camera: Add support to handle CIO2 device
This change updates mipi_camera driver to handle CIO2 device type.

Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42470
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:44:42 +00:00
Matt Delco 1ffee9d7f1 drivers/intel/mipi_camera: SSDT changes to add PLD
This change updates mipi_camera driver to add PLD section to SSDT.

Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42469
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:44:33 +00:00
Matt Delco 964033f7d2 drivers/intel/mipi_camera: SSDT changes to add DSM
This change updates mipi_camera driver to add DSM section to SSDT.

Change-Id: Ic60e972b6aebad171a7b77fe0d99781693adfb20
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42468
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:44:22 +00:00
Matt Delco 1245b1e098 drivers/intel/mipi_camera: Add support for camera sensor in SSDT
This change updates mipi_camera driver to handle camera sensor.

Change-Id: I581c9bf9b87eac69e88ec11724c3b26ee5fa9431
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42467
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:44:15 +00:00
Matt Delco c3a83bf514 drivers/intel/mipi_camera: Handle NVM and VCM device type
This change adds support in mipi_camera driver to handle NVM and VCM
device types.

Change-Id: I24cb7f010d89bc8d14e0b4c8fe693ba6e9c68941
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42466
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:44:06 +00:00
Matt Delco 7d00293af8 drivers/intel/mipi_camera: Handle acpi_name and common code
This change updates the mipi_camera driver to handle acpi_name based on
device_type, if acpi_name is not set in the devicetree and moves some of
the common code to separate methods.

Change-Id: I15979f345fb823df2560db269e902a1ea650b69e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 14:43:45 +00:00
Benjamin Doron c01fa5ad5d util/inteltool: Support dumping more BARs on Skylake mobile SoCs
Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y.
These chipsets are similar to others supported by the tool.

Working on SKL-U.

Change-Id: Ic43d54ef189d500701872a56e67781a744990328
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-07 08:56:13 +00:00
Chris Wang 4ab0db2d27 mb/google/zork: update telemetry settings for dalboz
update telemetry value for SDLE test result.

BUG=b:152922299,b:152369472
TEST=emerge-zork coreboot

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42999
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 08:56:03 +00:00
David Wu ae5679366b mb/google/volteer/var/terrador: Update gpio settings and overridetree.cb
Based on schematic and gpio table of terrador, generate gpio settings
and overridetree.cb for terrador.

BUG=b:156435028,b:151978872
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Verify that the image-terrador.bin is generated successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 04:44:07 +00:00
David Wu 887c1f1daf mb/google/volteer/var/terrador: Add memory parts and generate DRAM IDs
This change adds memory parts used by variant terrador to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.

Added memory
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E

BUG=b:159195585,b:152936481,b:156435028
TEST="emerge-volteer coreboot chromeos-bootimage", flash terrador and
verify terrador boots to kernel.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41995
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07 04:19:10 +00:00
David Wu d964fea5a6 lp4x: Add new memory parts and generate SPDs
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E

BUG=b:159195585,b:152936481,b:156435028
TEST=build.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-07 04:18:55 +00:00
Ravi Kumar Bokka cdd84e7f62 trogdor: Add board variant checks in Kconfig
Diffentiate Lazor and trogdor build configuration

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42730
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 23:53:45 +00:00
Anna Karas 072a9b96eb tests: Add lib/b64_decode-test test case
Implement unit tests for lib/b64_decode module.

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Id5fe9272e30eaff3d086a95241b3819101089c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42313
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 23:47:40 +00:00
Anna Karas 907ddc3e07 tests: Complete lib/string-test test case
Implement unit tests for remaining string library functions. Fix memory leak
in test_strdup().

Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I8ac6a6b2413d9077dc9ea81f638a2b0acd5c8862
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42311
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 23:47:27 +00:00
Angel Pons 9ce5bee8c0 sb/intel/i82801jx/sata.c: Handle ABAR as a resource
Instead of directly reading ABAR without any checking, do like i82801ix
and treat it as a resource. This prevents problems if ABAR is not set.

Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06 23:34:21 +00:00
Angel Pons 6ab28b465a src/**/acpi/smbus.asl: Drop dead code
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.

Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-06 23:11:08 +00:00
nick_xr_chen f446b81f8f mb/google/volteer: Enable HotPlug on PCIe root port for the SD express
Enable HotPlug for the PCIe root port that the SD express is on so the
OS can re-train the link without needing a reboot if it goes down
unexpectedly at runtime.

BUG=b:156879564
BRANCH=master
TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in
linux that it is identified as a HotPlug capable root port

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 20:32:11 +00:00
Angel Pons d9dea65615 soc/intel: Drop unused `#include <reg_script.h>`
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.

Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-06 19:29:07 +00:00
Patrick Rudolph 7d28f20051 pgtblgen: Update comment to match what the code does
Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-06 17:24:59 +00:00
Kyösti Mälkki b2a10f8264 devicetree: Remove weak declarations for ops
Make it compulsory to build with all the drivers that are
visible in the board devicetree.cb file.

Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-06 16:11:02 +00:00
Kyösti Mälkki 18d41e1c45 mb/amd/mandolin: Drop SPD eeproms in devicetree
Even with previous platforms, these entries were not
utilised for raminit.

Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-06 15:18:52 +00:00
Nico Huber 06b68d1097 prog_loaders: Fix ramstage loading on x86
A regression sneaked in with 18a8ba41cc (arch/x86: Remove RELOCATABLE_
RAMSTAGE). We want to call load_relocatable_ramstage() on x86, and
cbfs_prog_stage_load() on other architectures. But with the current
code the latter is also called on x86 if the former succeeded. Fix
that and also balance the if structure to make it more obvious.

TEST=qemu-system-x86_64 boots to payload again.

Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43142
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 09:36:15 +00:00
Patrick Georgi 8008c530e7 mb/google/volteer: Rename remaining pmc_mux/con to conn
CB:43090 renamed con to conn to avoid issues when building on Windows.
CB:42905 introduced more uses of the old name.

Adapt the latter to comply with the former.

Change-Id: I723141add5452fc541f67cb8591793f2d64cc231
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 09:35:52 +00:00
Keith Hui 698647a8c0 mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate
PS/2 keyboard and mouse devices are declared twice in the DSDT, once
in mainboard and once in southbridge. It would appear in Windows
Device Manager as two PS/2 keyboards and two PS/2 mouses, all with
resource conflicts. This change drops the declaration from mainboard.

The issue was discovered when this setup was copied for p8z77-m and
being boot tested.

Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41225
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:30:56 +00:00
Paul Menzel 01c1815eae drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO
As the booting the system can be delayed for a noticeable amount of
time, often 60 seconds is the default, this is not a debug message.
Chose log level BIOS_INFO.

Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-06 06:30:14 +00:00
Keith Hui 572d66abb6 nb/intel/i440bx: Add PMCR register to ACPI code
p3b-f suspend code is going to use it.

Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:27:36 +00:00
Keith Hui 8ba85deb8f nb/intel/i440bx: Refactor ACPI code
Bring DRB7 OpRegion and top-of-memory indicator inside NB device.

Use more concise ASL 2.0 syntax for TOM calculations.

Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-06 06:26:55 +00:00
Keith Hui 562279e6ca sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS
Only two mainboard groups use this southbridge:

emulation/qemu-i440fx: Nothing creates or consumes this ACPI path.
asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O
resources, which are being declared in DSDT.

It is not doing anything useful and causes ACPI errors in Linux
kernel[1][2], so it has to stop.

[1] https://review.coreboot.org/c/coreboot/+/38601
[2] https://review.coreboot.org/c/coreboot/+/38304

Change-Id: I770047610e02c08191613b57c989b3bc1d464684
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06 06:23:44 +00:00
Arthur Heymans c73ad35e39 mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS
Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06 06:19:30 +00:00
Kyösti Mälkki 18a8ba41cc arch/x86: Remove RELOCATABLE_RAMSTAGE
We always have it, no need to support opting-out.

For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage
located inside CBMEM, which is only true with ARCH_X86.

Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:17:47 +00:00
David Wu 7c040adc8c mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb
Based on schematic and gpio table of voxel, generate gpio settings
and overridetree.cb for voxel.

BUG=b:157879197,b:155062762
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Verify that the image-voxel.bin is generated successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06 06:15:27 +00:00
Julius Werner 63358eaff6 libpayload: cbgfx: Fix add_fractions() overflow reduction
log2(1) is 0 and log2(0) is -1. If we have the int64_t 0xffffffff then
log2(0xffffffff >> 31) = log2(0x1) = 0, so the current reduction code
would not shift. That's a bad idea, though, since 0xffffffff when
interpreted as an int32_t would become a negative number.

We need to always shift one more than the current code does to get a
safe reduction. This also means we can get rid of another compare/branch
since -1 is the smallest result log2() can return, so the shift can no
longer go negative now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06 06:14:57 +00:00
Chris Wang a94136f082 mb/google/zork: Apply cereme telemetry settings for dalboz
Currently, the telemetry settings are not for the pollock platform
and might causethe power and performance issue. so applied the Pollock
reference board settings to Dalboz to improve the performance,
and the values need to be updated after the SDLE test finished.

BUG=b:157961590,b:152922299
TEST=Build.

Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:14:31 +00:00
Chris Wang 1e3e528d23 mb/google/zork: Apply USB2 default phy tune parameter for Zork family
Apply the default USB2 phy tuning parameter for Zork family

BUG=b:155132211
TEST=Build, verified the default value been applied on trembyle
and the USB2 device works well.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I1f00b04173796d70147e232bafa405487b0761e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:14:17 +00:00
Chris Wang 04dfc26f94 mb/google/zork: Add USB2 phy tuning parameter for SI tuning
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.

BUG=b:156315391
TEST=Build, verified the tuning value been applied on Trembyle.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:14:07 +00:00
Caveh Jalali 6e62223f01 mb/google/volteer: Add support for passive USB-C daughterboard
The USB-C SBU and HSL orientation configuration depends on the USB
daughterboard used on the system. This patch adds an additional
configuration for supporting passive USB daughterboards using "probe"
directives to select the appropriate configuration at runtime.

BUG=b:158673460
TEST=verified active USB DBs enumerate at USB3 speeds in linux

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-06 06:12:14 +00:00