Cleanup to make the file follow the same convention after USE_MTCL was
added and the depends structure was requested instead of the if guards.
Signed-off-by: David Ruth <druth@google.com>
Change-Id: I3604b394f999b28de4723337b3b6b4e21139c83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT for MediaTek WiFi chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets.
Change Summary:
* Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related
to MTCL
* Add write_mtcl_aml function to convert the byte data into the format
expected by the MTCL functionality in the Linux kernel.
* Add validate_mtcl function to validate that the byte data read in
from a file is in the expected format.
* Add write_mtcl_function function to read a binary file called
"wifi_mtcl".bin" from cbfs, then call validate_mtcl to verify that
it is in an expected format, and if so write the aml via acpigen
* Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order
to include MediaTek WiFi specific functionality
* Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and
enables including the specific ACPI function defined in SSDT
* Add config flag CONFIG_MTCL_CBFS_FILEPATH which depends on
DRIVERS_MTK_WIFI which enables configuring the file to add as
"wifi_mtcl.bin"
* Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c
to include the MTCL function in SSDT for MTK WiFi devices when
USE_MTCL is enabled.
* Add MediaTek VID to src/include/device/pci_ids.h.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.bin blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth@chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80170
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Currently, SOC_INTEL_COMMON_BLOCK_TCSS will set MUX to disabled. The two
related options to re-configure it for either USB devices or displays,
are currently only supported by the ChromeEC. As such, any device
without the ChromeEC will boot with attached USB-C devices in a
non-functional state.
Add TCSS_HAS_USBC_OPS to make this feature configurable, and set the
default to enabled if the board features the ChromeEC.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79882
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is just a clean-up commit.
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the I2C configuration to match the usage such that only required
I2C controllers are enabled.
BUG=b:319390850
TEST=Build Brox BIOS image and boot to OS. Ensure that only the required
I2C controllers are enabled.
Change-Id: I9f24beb9ef587163362cc6ded88efb05be1329b9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80303
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a memory leak fix in Linux 6.7.
Change-Id: I1ff302dafa01e78429a30ff18e21ffe0b45ce46e
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80263
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Follow reference design rex0, keep the GPIO settings of CNVi/PCIe.
Only set GPP_F04,GPP_F05/GPP_S01,GPP_S02 to NC when
WIFI_PCIE/WIFI_CNVI is selected.
BUG=none
TEST=Build and test on karis
Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update element "KB_TYPE_CA" for align fw_config.
Only EC will reference KB_TYPE field in fw_config. This
CL is just for align fw_config.
BUG=none
TEST=emerge coreboot pass
Change-Id: Ied54f78dddd9dddca1272fc31c9502fc11c61dde
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
This patch switches the cbmem utility from its own IP checksum
implementation to the commonlib version (which is good because the old
one had a couple of bugs: doesn't work on odd sizes and may overflow
its carry accumulator with input larger than 64K).
Change-Id: I0bef2c85c37ddd3438b7ac6389e9daa3e4955b31
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80256
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a bit of optimized assembly code to the ipchksum()
algorithm for x86 targets in order to take advantage of larger load
sizes and the add-with-carry instruction. The same assembly (with one
minor manual tweak) works for both 32 and 64 bit mode (with most of the
work being done by GCC which automatically inserts `rax` or `eax` in the
inline assembly depending on the build target).
Change-Id: I484620dc14679ff5ca02b2ced2f84650730a6efc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80255
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a bit of optimized assembly code to the ipchksum()
algorithm for arm64 targets in order to take advantage of larger load
sizes and the add-with-carry instruction. This improves execution speed
on a Cortex-A75 by more than 20x.
Change-Id: I9c7bbc9d7a1cd083ced62fe9222592243a796077
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Yidi Lin <yidilin@google.com>
This patch moves libpayload over to the commonlib implementation for
calculating the IP checksum.
Change-Id: Ie8d323ce9f8d946758619761b4b22d54bce222b6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80253
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Yidi Lin <yidilin@google.com>
This patch adds a few more test cases for the IP checksum algorithm to
catch more possible corner cases (large data with more than 64K carries,
unaligned data, checksum addition with offset, etc.).
Change-Id: I39b4d3f1bb833894985649872329eec88a02a22c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
This patch moves the IP checksum algorithm into commonlib to prepare for
it being shared with libpayload. The current implementation is ancient
and pretty hard to read (and does some unnecessary questionable things
like the type-punning stuff which leads to suboptimal code generation),
so this reimplements it from scratch (that also helps with the
licensing).
This algorithm is prepared to take in a pre-calculated "wide" checksum
in a machine-register-sized data type which is then narrowed down to 16
bits (see RFC 1071 for why that's valid). This isn't used yet (and the
code will get optimized out), but will be used later in this patch
series for architecture-specific optimization.
Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Make the initialization of the IOAPIC(s) in the PCI root(s) common
across all AMD family 17h+ SoCs. For this the more general
implementation from the Genoa code that supports multiple PC roots is
moved to the common AMD code. All other family 17h+ SoCs are then
adapted to use the common code. For those non-Genoa SoCs, the
initialization of this second IOAPIC is moved from the northbridge
device to the domain device above to match Genoa.
Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized
on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL
based Phoenix SoC code. Since the Phoenix chip.c is different due to
some FSP-specific data structures in there that are guarded in the
openSIL case, a separate devicetree for the openSIL case is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Since the USB configuration data structure is FSP-specific, add guards
on this part of the soc_amd_phoenix_config struct and the corresponding
include.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6c324421fbc3dc7b9a7bf6f5868785e9718147a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80298
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since openSIL configures the APCI IO port addresses, coreboot should not
overwrite them.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80297
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the calls to the openSIL stubs to do the silicon initialization, to
get the APCI IO ports, and to get the memory map.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80296
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The configuration of the PCIe clock generators in the FCH was moved from
the FSP to coreboot, since all registers are documented. This
initialization is however tightly integrated in the rest of the PCIe
init code inside the reference code. In the FSP case, this code was
manually removed. openSIL will do that part of the initialization so
that there's no coreboot-specific change needed in openSIL. This will
also avoid the problems caused by mismatching configurations done by the
coreboot code and the PCIe init part of the reference code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
In the FSP case we get this info via a HOB. It's currently unclear if
we'll get a data structure for this from openSIL or if we'll end up
being able to just read the configuration fro the hardware, so add a
get_pci_routing_table stub for now to be able to build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Add the SOC_AMD_PHOENIX_OPENSIL Kconfig option to be able to build the
Phoenix code using openSIL instead of FSP for initializing the hardware.
Since there's currently no publicly available openSIL code for Phoenix,
SOC_AMD_OPENSIL_STUB is selected to have the stubs added to the build
instead of the actual openSIL code. The code added by selecting
SOC_AMD_COMMON_BLOCK_ACPI_CPPC relies on getting the information it
needs via a HOB, so for only select that option in the FSP case for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If597ff3dc824ce832399d3efde32352b36354b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a stub implementation of the openSIL interface between coreboot and
vendorcode. This can be used to add most of the coreboot-side support
for a SoC using openSIL without the actual opnSIL code already being
publicly available. Once the corresponding openSIL code is available,
the SoC can then switch over to using the actual openSIL implementation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80292
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Remove the unused soc/platform_descriptors.h include and add the missing
types.h include.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0b066aa5dc657f7709f9cce734a025180bf5bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Rename the BOARD_AMD_BIRMAN_PHOENIX option to
BOARD_AMD_BIRMAN_PHOENIX_FSP to distinguish between the FSP-based SoC
initialization and the non-FSP based one. Also change the
MAINBOARD_PART_NUMBER string to 'Birman_Phoenix_FSP'.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3293a07cd1b1833df15ee0a40cad3127e19b7df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The last 'endif' belongs to the 'if BOARD_AMD_BIRMAN_COMMON' in line 26,
so fix the comment. Commit 35a30de7af ("mb/amd/birman: Use common
option for variant configuration") changed that condition, but missed
updating this comment, so do this now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I986e5a456e8f9fd92aacd007479c861feea06199
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Only add the vendorcode/amd/fsp/phoenix and vendorcode/amd/fsp/common
folders to the include search path when the SOC_AMD_PHOENIX_FSP Kconfig
option is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80288
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide 3 separate functions for each openSIL time point instead of one,
so that we don't need the xSIM-api header file to be included in
opensil.h to decouple the coreboot code more form the openSIL code. This
will allow to create an openSIL stub implementation to already get most
of the coreboot-side SoC code in place before the openSIL source code is
done and released.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
When a device with no resource is passed it will keep overwriting
the current slot. Remove the conditional and allow a PCI device
to not have any resources.
This is particular useful for the next commits that makes use
of the PCI resource store to pass UBOX devices to SMM that allow
to lock-down SMM from within an SMI handler. Those devices do
not have any resources and cannot be hardcoded in SMM as their
PCI segment group and bus number varies depending on socket
count, CPU discovery and configuration.
Change-Id: I1a1b5944c97da5be6b9794c653b5159683f492e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80246
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Commit d252776668 ("tree: Replace And(a,b) with ASL 2.0 syntax")
replaced two instances of `And(var, mask) == 0` with `var & mask == 0`.
This expression needs parentheses - `(var & mask) == 0`.
Without parentheses, it is always false, since the masks are nonzero
(`var & (mask == 0)`; `var & 0`; `0`).
This caused brightness changes on Intel GMA to take longer than
normal since the status was never checked. The brightness would
change immediately, but another brightness change could not occur until
the first change timed out.
This was most noticeable in KDE, which waits for the brightness change
to complete before accepting another brightness up/down keypress.
Tapping brightness up/down repeatedly would take much longer to reach
max/min brightness due to many presses being ignored.
It is noticeable in GNOME as well but less obvious. Tapping brightness
up/down repeatedly would handle all keypresses, but the display's
actual brightness would lag behind and skip some intermediate steps.
I tested both Librem 13v2 and Librem 14, as far as I know this would
apply to all systems configuring brightness with Intel GMA.
Test: Verify brightness keys respond quickly again on Librem 13v2 / 14.
Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80260
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds support for the new command-line option `-E` to
the ifdtool, which enables users (primarily factory users) to
protect GPR0.
Additionally, this patch refactors some code while adding support for
enabling GPR0 protection.
For more information on the scope of GPR0 (General Protection Range 0),
please refer to the Intel Meteor Lake-U Type 4 Client Platform SPI
Programming Guide, Document Number 768150.
BUG=b:270275115
TEST=Able to test GPR0 protection on google/rex and google/yahiko.
> ifdtool -p mtl -E image.bin -O image.bin_lock
...
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
...
GPR0 protection is now enabled
Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
On Brox, HDA Codec used is ALC256. Add verb table for the same. Also,
add the related device tree changes for HDA related registers.
Realtek High Definition Audio Configuration-
Version : 5.0.3.1
BUG=b:317398558
BRANCH=None
TEST=verified HDA on Brox.
HDA Sound cards detected. Headphone working verified.
Device listed under sysfs as below:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ID 256
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek
Change-Id: I1edd5aee053debe39b34048266703031c088cd00
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79723
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the SoC-specific memory map is reported on the domain device
instead of the northbridge device, factor out the
read_soc_memmap_resources function from root_complex.c to new memmap.c
file. For now each SoC still has its own memmap.c file, but the plan is
to eventually have a common implementation that works for all AMD family
17h+ SoCs. For that I'll still need to look closer into the differences
between the FSP and the openSIL integration though.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Only call read_fsp_resources if PLATFORM_USES_FSP2_0 is selected in
Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic63e0904ad04dbecfac1be4d59abbb8d4f9f11d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the
legacy PCI config space access is needed on all AMD SoCs, implement a
common add_pci_cfg_resources function that reports both and gets called
from amd_pci_domain_read_resources and don't report those in the SoC-
specific code any more. The only functional change is that on Genoa now
the IO ports used for the legacy PCI config space access get reserved.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
To make add_opensil_memmap match the other function that are directly or
indirectly called by amd_pci_domain_read_resources, pass the resource
index as a pointer instead of passing it by value and then returning the
new resource index.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Introduce read_soc_memmap_resources which gets called by
amd_pci_domain_read_resources for the first domain of the SoC to report
the DRAM and PCI config space access resources to the allocator. For
Genoa this allows to use amd_pci_domain_read_resources as read_resources
in the genoa_pci_domain_ops instead of needing to wrap that call to be
able to call add_opensil_memmap for the first domain. For the other
family 17h+ SoCs the moves the reporting of the DRAM resources and the
PCI config space access resources from the northbridge device to the
domain device.
TEST=Resources still get reported on Mandolin, but now under the domain
instead of the northbridge PCI device
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib19fd94e06fa3a1d95ade7fafe22db013045a942
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80268
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use an unsigned long as resource index type instead of an int to match
the data type used for the index in the resource struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f58e32a535326116460545287cc59aaf94166a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Use an unsigned long as resource index type instead of an int to match
the data type used for the index in the resource struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60ac0e30627001698565b7256421780f9a94bf65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80266
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Use an unsigned long as resource index type instead of an int to match
the data type used for the index in the resource struct and the
functions to report the resources.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80265
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously the code checked if the first downstream bus of the domain
was bus 0 in segment group 0 to only run certain code for the first
domain. Instead check if the domain number is 0 which should make the
code a bit easier to understand.
TEST=add_opensil_memmap still gets called exactly once on Onyx
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of manually crafting S:B:D:F numbers for every
VTD device loop over the entire devicetree by PCI DEV IDs.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80092
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Attach UBOX stacks on newer generation Xeon-SP.
In order to use PCI drivers for UBOX devices, locating UBOX devices
by vendor and device IDs and replacing device access by specifying
S:B:D:F numbers, add a PCI domain for the UBOX stacks and let the
PCI enumerator index all devices.
Since there are no PCI BARs on the UBOX bus the PCI locator doesn't
have to assign resources on those buses.
Once all PCI devices on the UBOX stack can be located without knowing
their UBOX bus number and PCI segment the Xeon-SP code can fully
enable the multi PCI segment group support.
Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID.
Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80091
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The x86 core always starts with an IP at 0xfff0. This needs to match in
the code.
Change-Id: Ibced50e4348a2b46511328f9b3f3afa836feb9a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Allow SMM to verify the list of provided PCI devices by comparing
the device and vendor ID for each PCI device.
Change-Id: I7086fa450fcb117ef8767c199c30462c1ab1e1b6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Only call amd_fsp_silicon_init if PLATFORM_USES_FSP2_0 is selected in
Kconfig. I'm not 100% sure about the data_fabric_set_mmio_np call yet,
but since it doesn't depend on PLATFORM_USES_FSP2_0 to compile, I'll
look into that one later.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Fix spelling mistake added in 3e99ba0 "device: Add a helper function to
add a downstream bus".
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I66ae5000f6f5c0e5bfe42bdfbbbcedec6df0c520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80234
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
David Ruth