The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch adds initial romstage code and spd data for LP5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 LPDDR5
Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B
Board ID -
0b0000 - Empty spd hex file
0b0001 - DDR5 (Empty spd hex file)
0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B)
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: I15b352eb246aed23da273e56490c7094eae9d176
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Marasov variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:264838335
TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS
during boot path.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Intel SPR-SP processor has socket type as
PROCESSOR_UPGRADE_SOCKET_LGA4677 which is different
from the socket type of CPX-SP and SKX-SP.
Change-Id: Id2279cc0c1fa3f007d7c081af6f78e5aa98d2f3d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71947
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we support >1 Xeon-SP, XEON_SP_COMMON_BASE no longer
reflects the socket type. This uses SOC_INTEL_* Kconfig variables and
returns the correct socket type for Cooper Lake-SP.
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I142de5f040f3b76e352f27c00fe9e50787df5712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training
data after FSP-S instead of FSP-M. For now only SPR-SP server
FSP supports this.
This issue surfaces with SPR-SP, because of the memory type
(DDR5 support) and memory capacity (more memory controllers, bigger
DRAM capacity). Therefore Intel decided to save MRC training data after
FSP-S with SPR-SP FSP.
Change-Id: I3bab0c5004e717e842b484c89187e8c0b9c2b3eb
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71950
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PMC registers are quite different between LBG and EBG. Move pmc.h
to lbg directory to differentiate.
Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This functionality is used in multiple places, so factor it out into a
function. Compared to acpigen_write_processor_cnot, the buffer size is
decreased from 40 to 16 bytes, but the format string specified by
CONFIG_ACPI_CPU_STRING results in 9 chars and a NULL byte which will fit
into the buffer without any issue. I've seen the CPU devices being put
into another scope within \_SB, but even in that case that would be 14
chars and a NULL byte whist still fits into the 16 byte buffer. For
acpigen_write_processor and acpigen_write_processor_package this doesn't
change any edge case behavior. In the unrealistic case of the format
string resulting in a longer CPU device string, this would have been a
problem before this patch too.
Also drop the curly braces of the for loop in
acpigen_write_processor_package. This makes the code a bit harder to
read and isn't a very good idea, but with the curly braces in place, the
linter breaks the build :(
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d8291a2aaae2011cb185d72c7f7864b6e2220ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72452
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
ACPI_CPU_STRING specifies the format string for the scope of the
processor devices in the generated ACPI code. Also point out that the
resulting string will be truncated to at most 15 chars to fit into the
16 byte buffer used in two functions in acpigen.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fb1db8adeecd783c835a500d28a13b823cda155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72451
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Not all Chrome-EC devices have a keyboard or use Vivaldi for key
remapping, so demote the printk output when the EC doesn't support
it from ERROR to INFO. Adjust the printk text for clarity.
Change-Id: I14059f4e3e56ff891f302601d5acc1bb842cffc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72474
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The comment in the header amdfwtool.c was written long time ago and is
needed to get updated.
Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The current CMOS option causes Linux to not boot, as the GRUB EFI
loader will report an incorrect parameter.
Update the CMOS option so that the corresponding UPD is changed when
the wireless is set to disable, so that the root port for the wireless
is also disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I607d700319d6a58618ec95b3440e695c82dff196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the Type-C USB 2.0 interface to a standard port, as the
Type-C macro will not work in Linux (dmesg says the cable is
faulty),
This makes the port work reliably in Linux, tested with:
* Manjaro 21
* Ubuntu 22.04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions that allow checking and changing PTT state at runtime.
Can be useful for platforms that want to use dTPM instead and have no
means to stitch ME firmware binary with disabled PTT.
The changing function also checks for the current feature states via
HECI to ensure that the feature state will not be changed if not
needed.
TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
BUG=b:239110778
TEST=Make sure that the output of elogtool is unaffected by this change.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia1a6341abd834dd9ad5f12c9f2eefb0489364a08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72099
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return generic coreboot error codes from the mb_adjust_cfg
callback used in mainboards instead of '-1' constant and
a driver-specific success-indicating define.
BUG=none
TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3
build correctly.
Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The D-state list lists the devices with the corresponding
D-state that the devices should be in, in order to enter LPM
DPTF is not mentioned in Intel's document 595644 as one of
the devices.
This CL removes it to avoid an error seen after it was added
to that table:
"ACPI Error: AE_NOT_FOUND, While resolving a named reference
package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)"
TEST=Built and tested on anahera and saw the error is gone
BUG=b:231582182
Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Depending on the actual issue and the experience of the contributor,
"Easy projects" might not be an appropriate description for Coverity
issues and similar things.
Thus rename this section to "Small projects" and also update references
to it.
Change-Id: I3bdefd9f37440ab3ae493095b7fb5c76394d2ba1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72447
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
add functions for concatenate OP
add debug message containing concatenated string with string, value, or
OPs
Ex1: to print string with another string provided from C side:
acpigen_write_debug_concatenate_string_string("Wait loop Timeout! var=",
name, LOCAL6_OP);
will generate:
Concatenate ("Wait loop Timeout! var=", "L23E", Local6)
Debug = Local6
Ex2: to print string with a value:
acpigen_write_debug_concatenate_string_int("ModPHY enabling for RP:",
pcie_rp, LOCAL0_OP);
will generate:
Concatenate ("ModPHY enabling for RP:", 0x05, Local0)
Debug = Local0
Ex3: to print string with an ACPI OP:
acpigen_write_debug_concatenate_string_op("while Loop count: ",
LOCAL7_OP, LOCAL6_OP)
will generate:
Concatenate ("while Loop count: ", Local7, Local6)
Debug = Local6
TEST=Add above functions in the acpigen code and check the generated
SSDT table after OS boot
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I370745efe3d6b513ec2c5376248362a3eb4b3d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl5 and observe that POST codes are
displayed before DRAM training.
Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Update the notes for the 4.19 release.
- Add the intel/icelake_rvp board as being supported on the 4.19 branch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5c283f64efc465d8f70fc19d570c5b7547474e80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72481
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The Alder Lake PEIM graphics driver executed as part of the FSP does
not wait for the panel power cycle to complete before it initializes
communication with the display. It can result in AUX channel
communication time out and PEIM graphics driver failing to bring up
graphics.
If we have performed some graphics operation in romstage, it is
possible that a panel power cycle is still in progress. To prevent any
issue with the PEIM graphics driver it is preferable to ensure that
panel power cycle is complete.
This patch replaces commit ba2cef5b54
("soc/intel/common/block/early_graphics: Introduce a 200 ms delay")
workaround patch.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible in the recovery flow
Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
We were using the libgfxinit `Initialize' function with the
`Clean_State' parameter because the more appropriate `Update_Output'
function was not performing all the necessary clean up operations for
the PEIM driver to be successful when libgfxinit was used in romstage.
Thanks to a lot of experiments and some log analysis efforts, we were
able to identify the missing operation and fix the `Update_Output'
function (cf. https://review.coreboot.org/c/libgfxinit/+/72123).
The `initialized' global variable is now unnecessary as we track the
initialization in the Ada code instead.
Since the `Update_Output' function does not return any value, this
patch modifies the `gma_gfxstop' prototype accordingly. This does not
have any impact as the return value was not used anyway.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible
Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch restricts the dump of the vebose graphics output settings
to configuration with the `DEBUG_ADA_CODE' flag set.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Configuration dump is seen only if DEBUG_ADA_CODE is set
Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72418
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add info on where to contribute to Dasharo.
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I1b7e7aa05a0cabc990bddfaf957873402ebe183f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
CLKREQ Pins are intentionally not configured, because there seems to be
a current Issue with FSP, that causes pci devices to not work if CLKREQ
Pins are configured by coreboot. The msi/ms7d25 mainboard seems to have
a similar issue and the cause is also documented in it's gpio.c file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba35076af194de0e85de60ebc93d62fda24e9c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add the remaining DDR2 code to program the registers for memory
timings, ODT, RCOMP, and refresh mode; and perform receive-enable
calibration.
TEST: DDR2 systems boot
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I6d9a1853fea9e29171d7c2f9ffe7086685c9efad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move DDR3 memory I/O init to its own function and add DDR2 memory I/O
init. Read I/O init is common to both DDR2 and DDR3.
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: Ic4d5130f527249d3a5b98bae778cdf21a1753b04
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Split JEDEC init into common and DDR3 specific parts and add the DDR2
specific init code. This also replaces raw `mchbar_clrsetbits32` calls
with a dedicated `jedec_command` function.
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I7a57549887c0323e5babbf18f691183412a99ba9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial support for DDR2. This also changes GM45 raminit to
internally work in units of 1/256 ns for both DDR2 and DDR3 instead of
the 1/8 ns MTB assumed for DDR3, which simplifies the handling of time
values. DDR3 time values are thus scaled by a factor of 32 accordingly.
TODO:
- DDR2 JEDEC init
- Memory IO init
- Register programming
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I265938d58c30264fd5d4f7b89da7b689058b8cf8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the `hyper_threading` CMOS option from most boards, as it's most
likely not working properly and causing problems. The main reasons to
remove the option are:
* The used enum is backwards (0 ---> Enable, 1 ---> Disable)
* Platform/SoC code does not honor the `hyper_threading` option
Also, remove the now-unused enum used by the `hyper_threading` option.
Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Enable pin 0x18 which is used for the 3.5mm combo jack microphone
detection.
Also, disable 0x17 as it is not used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I05856627c073acaff49ea1ddc048a49a74b6268f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71718
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Getting an error from the Kernel on Rex devices:
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI (20210730/dspkginit-438)
FSPI is defined in src/soc/intel/meteorlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
See commit feed8e4bd9 ("soc/intel/adl/acpi: add FSPI to DSDT") for
the corresponding ADL CL.
TEST=Built and tested on brya by verifying the error is gone.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id8d2a1b5e074f036345e028b117d420bf36a9042
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This function reads out the current value set to output for a GPIO pin.
Ex: GPP_E0 is set to output
int e0_val;
e0_val = gpio_tx_get(GPP_E0);
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Fix the comment as "checkpatch" says.
Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Current size of the cbmem premem buffer (8KB) is sometimes insufficient
to contain the complete debug log causing the cbmem console buffer to
indicate overflow.
This patch increases the premem cbmem buffer size to 16KB so that
the complete debug log can be stored in it.
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before, the Intel HDA PCIe device was showing up in the lspci tool, but
Audio wasn't working.
This patch enables the corresponding FSP-M settings to make it work.
Tested on Prodrive Atlas with Themis carrier board on Windows 10 and
Linux 6.1.0-rc3.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I144618c453c1e6a3e759afc7532a4ac4a71814c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently ASPM cannot be disabled by individual mainboards, if the
soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like
PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by
individual mainboards if needed. This change makes PCIEXP_ASPM one of
these configurable options.
Test: build prodrive/atlas and see that build/config.h lists the
option CONFIG_PCIEXP_ASPM as disabled.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to the
device and since the bridge doesn't have enough MMIO space reserved, the
Linux kernel can't assign resources to it. To fix this problem, enable
the mp2 device in the mainboard's devicetree so that it gets its
resources assigned by coreboot. An equivalent change was verified on
Chausie.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Arthur Heymans