This reduces boilerplate. One functional difference is that SSDT no
longer has oem_revision set to 42.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Adding tables to R/XSDT, aligning current pointer, computing checksum is
a lot of boilerplate that needs to be done for each table.
TESTED on foxconn/g41.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Phoenix is an x86 soc that supports sha256 instructions.
TEST=boot birman to chromeos
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id228399ba02708b97110d524ce12c2626588762d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76166
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Always send the Exit 4-Byte Address Mode (E9h) command before the first
access to the SPI flash in all stages when the SPI flash is
memory-mapped. This is useful for x86 mainboards that do not access SPI
flash in bootblock yet still need to exit 4-byte addressing mode in
romstage or ramstage.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace `CBFS_SIZE` with FMD files to declare regions and sizes. This
will be used to lock BIOS region (except SMMSTORE) on boot.
`CBFS_SIZE` was incorrectly set to 10 MiB, so this also corrects the
BIOS region size to match the FIT values.
Change-Id: I0f068f4d9b376f12b46faa5bb0c6a08e6cb744d8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76155
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Fixes building when `USE_OPTION_TABLE` is selected.
Change-Id: I4fb017aa549b24eda6b9e0356bc1776d4044c95d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Multiple users have requested to have the DMI values for product UUID
and serial number be populated. Enable the drivers so that we may set
them when flashing or updating firmware.
Change-Id: I710363d9df626d51756a265f0099f26ef28411c2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
The Infineon chip occasionally fails Startup or Resume. Adding the
delay makes it work more reliably.
Change-Id: I4a8f98633154888e2167a3d55192b86e13ffcb62
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76095
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System76 EC since system76/ec@99dfbeaec3 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 values from
coreboot since they won't be used.
Ref: https://github.com/system76/ec/pull/353
Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Resetting the device will cause the keyboard backlight and airplane LED
to lose their state.
Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the EC to detect C10 using eSPI instead of a dedicated pin.
Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable D3cold to prevent issues with Thunderbolt not working after S3
suspend.
Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Move this function to the root Makefile.inc since other Makefiles use
the exact same function call. Will allow for deduplication in AMD SoC
Makefiles in a follow-on commit.
Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update SX9324 register settings based on tuning value from SEMTECH.
BUG=b:279510275
TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been decided not to use any of the USB 3.0 ports on this board.
This patch disables the remaining USB 3.0 port 0, after the port 1
has already been disabled in commit d0627c7595
("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1").
BUG=none
TEST=None of the USB 3.0 ports functional anymore after boot,
the USB 2.0 ports continue working.
Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the previous instruction the complete register was set to '0'.
Correctly, only the bits 23:16 must be masked.
Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.
Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3
refers to SATA port 1 only. To make this clear, change the name of the
define from 'TX_DWORD3' to 'TX_DWORD3_P1'.
Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
A correction of Tx signal from SATA interface is not necessary on these
boards currently. Therefore remove the define and the corresponding code
on mc_apl5.
Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table.
BUG=b:285477026
TEST=emerge-nissa coreboot and check the SAR value
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:283245785
BRANCH=firmware-grunt-11031.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the kb8010 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The kb8010 retimer does not support this
feature, so let the SoC do the flip.
BUG=b:267589112
TEST=verified DP-ALT mode works in both cable orientations on rex with
reworked kb8010 DB by flykt@
Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Secure OS was disabled on Grunt devices since it isn't used.
This reduces the attack surface and is meant to mitigate potential
security risks. However, this prevents users from using an alternate OS.
Enable Secure OS upstream to allows users to use Windows, and ensure
that it is still disabled in the chromium repo.
BUG=b:287630343
TEST=Builds with Secure OS included.
Cq-Depend: chromium:4620881
Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
New port based on autoport.
Autoport worked with minor tweaks, but fan speeds went almost
immediately to the maximum. They are controlled by the NPCD379
Super I/O which isn't supported by coreboot.
But coreboot already has code for NPCD378,
which HP Compaq 8200 SFF makes use of.
So SuperIO configuration was copied from the 8200 SFF port.
It seems to work without any issues in "normal" use.
Most importantly, fan speed control seems to work correctly.
However this means that some of the SuperIO LDNs may be configured
incorrectly. See the comments on Gerrit for more information.
The following is tested and is working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
* GRUB (with Libreboot config)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui
Untested:
* mSATA slot. The SATA port needs to be enabled on devicetree
too, but I'm unable to test due to lack of hardware
* Line in, mic input
* MXM graphics card
* EHCI debug
Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
maybe it just isn't present
* PS/2 keyboard wake from S3
Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- remove usb2_ports[5] since taranza doesn't have PL2303.
- add usb2_ports[6] and usb3_ports[1] for Type-A Port A4.
BUG=b:288094807, b:278167978
TEST=emerge-dedede coreboot chromeos-bootimage
verified all the USB port works
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7b411c21271497ba386143140aa8cfbb17a1a111
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76186
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch performs below operations to enable LAN0.
- Complete the LAN PEREST power sequencing
- Program the SRC_CLKREQ (GPP_D20) with correctly.
- Add overridetree.cb entry to configure the LAN0 device.
BUG=b:289395519
TEST=Able to boot google/ovis with LAN0 being enabled.
Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch performs below operations to enable LAN1.
- Add overridetree.cb entry to configure the LAN device.
- Complete the LAN1/SD PEREST power sequencing
BUG=b:289395519
TEST=Able to boot google/ovis with LAN1 being enabled.
Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the
Ovis schematics dated June'23 to ensure LAN port is not in sleep.
BUG=b:289395519
TEST=Able to measure SLP_LAN PIN and confirm it's deasserted.
Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis
schematics dated June'23 to ensure LAN ports having power.
BUG=b:289395519
TEST=Able to measure LAN port power is enabled with this CL.
Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
flashrom does not support libftdi 0.20 anymore and it's not used by
anything else. Its build systems (Makefile and Meson) only reference
libftdi1 and it still compiles fine without the legacy package. Thus,
drop it from the package list.
Change-Id: If1b575bc9abfd192e93811a83d8615bed61eba0c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
flashrom does not support libusb 0.1 anymore and it's not used by
anything else. Its build systems (Makefile and Meson) only reference
libusb1 and it still compiles fine without the legacy package. Thus,
drop it from the package list.
Change-Id: Ib9b7530e5b707e12fbf3f8058999456dc1f8dff4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The taranza removed the APW8738BQBI and "disable_external_bypass_vr" should be set to "1" to disable.
BUG=b:288978340
TEST=emerge-dedede coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I0a849fbfacba1d200c969c66bb058863d7ab3085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch updates the mux connection to reflect the Ovis schematics
dated June to ensure Type-C1 is able to work in DP-ALT mode.
BUG=b:289300284
TEST=Able to get display over Type-C1 port.
Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76149
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This was missed recently when adding the table. Linux complains about
the missing checksum, e.g.
[ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173)
Tested with QEMU/Q35, albeit with changes to the special handling for
ACPI with QEMU. The warning goes away.
Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 90464073e4 (acpi: Add SPCR table)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dimm_num shall be dimm, not channel.
BUG=b:288520486
TEST=In kernel, see output from `dmidecode -t 17`.
Observe that Locator reflects proper location of the module.
Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
In mtl, there is no MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
So, this patch removes unused code related to
MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
ADL also removes this code, see cl:62861
BUG=b:288976547
TEST=Tested on Screebo and DP/USB are working as expected after suspend/resume
Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76126
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds CPU ID for C0 stepping (aka QS).
DOC=#723567
TEST=Able to boot on C0 rvp (and rex) and get correct CPU Name in coreboot log.
Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83
Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76135
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ramstage.c in Makefile.inc and update Dibbi power limits in
Dibbi ramstage.c.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75681
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75680
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Eric Lai