Commit Graph

37617 Commits

Author SHA1 Message Date
Angel Pons 9f3bc37102 nb/intel/sandybridge: Correct designation of MRC version
Do not use `System Agent version` to refer to the MRC version, which is
what the register being printed contains under normal circumstances.

Change-Id: I8679bae37b8ccb76e9e9fc56fc05c399f6030b29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:10:20 +00:00
Angel Pons 7f454e4cbd nb/intel/haswell: Correct designation of MRC version
Do not use `System Agent version` to refer to the MRC version, which is
what the register being printed contains under normal circumstances. Use
the code from Broadwell, which also happens to be indented with tabs.

Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:10:12 +00:00
Angel Pons 1ca6b531ee nb/intel/haswell: Drop ASM to call into MRC
Commit c2ee680 (sandybridge: Use calls rather than asm to call to MRC.)
did it for Sandy Bridge, and this commit does it for Haswell.

Tested on Asrock B85M Pro4, still boots with MRC.

Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:51 +00:00
Angel Pons 0117e4eae3 nb/intel/haswell: Constify pointers to strings
Jenkins complains about it.

Change-Id: I20abdd01ca2b93e8a4de31664ff48651e7268d25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:41 +00:00
Angel Pons 6791ad221b nb/intel/haswell: Make MAD_DIMM_* registers indexed
This allows using the macro in a loop, for instance.

Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:32 +00:00
Angel Pons 6fe7986daf nb/intel/haswell: Drop unnecessary register read
Reading MAD_CHNL has no effect, so there's no need to read it here.

Change-Id: I8d2aa4787de7f54f49d161f61c9c0abaa811cb83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:12 +00:00
Angel Pons ac02814478 soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macro
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I013357d31974582f64a35b8228d9edfa16af99fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:04 +00:00
Angel Pons dd558fd0cf soc/intel/broadwell: Use common early SMBus code
Disabling interrupts and clearing errors was being done twice, once in
the `smbus_enable_iobar` reg-script, and another in `enable_smbus`.

Change-Id: I58558996bd693b302764965a5bed8b96db363833
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-23 18:08:51 +00:00
Angel Pons f2e2b9688e soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc init
Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:08:13 +00:00
Angel Pons 2436ac037b soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init
Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-23 18:07:35 +00:00
Angel Pons 6f44874598 soc/intel/broadwell: Drop reg-script from early SA init
Haswell does not use reg-script, but does more or less the same thing.
Adapt Broadwell to ease the eventual unification with Haswell.

Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:07:24 +00:00
Jason Glenesk 90f71918fb vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.h
Remove all typedefs and cleanup references to all structs and enums.

BUG=b:159061802
TEST=Boot morphius to shell.

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-23 16:28:26 +00:00
Kevin Chiu eef615c0f5 mb/google/zork: update telemetry settings for morphius
Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current.  Proper calibration is determined by the AMD SDLE tool
and the Stardust test.

VDD Slope: 62852 -> 62641
SOC Slope: 28022 -> 28333

BUG=b:170531252
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass AMD SDLE/Stardust test

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-23 16:27:19 +00:00
Rob Barnes a10229269a mb/google/zork/woomax: Adjust disconnect threshold
The disconnect voltage needs to be adjusted up because the HS DC voltage
level is 0xF.

BUG=b:170879690
TEST=Servo_v4 USB hub functions
BRANCH=zork

Change-Id: If8662015a45c57e457b4593e55af888084842f58
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-23 16:26:00 +00:00
Karthikeyan Ramasubramanian eef5cadca8 mb/google/dedede: Update the flash ROM layout for RW regions
RW_LEGACY region needs to be 1 MiB to accommodate any alternate
firmware. Hence update the flash ROM layout as below:
* Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to
  RW_LEGACY region so that it grows to 1 MiB.
* Remove VBLOCK_DEV region which is not used.
* Re-size the ELOG region to 4 KiB since that is the maximum size of the
  ELOG mirror buffer.
* Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that
  size is used in those regions.
* Resize SHARED_DATA region to 4 KiB since no more than that size is
  used in that region.
* Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB.

BUG=b:167943992, b:167498108
TEST=Build and boot to OS in Drawlat. Ensure that the firmware test
setup and flash map test are successful. Ensure that the event logs are
synced properly between reboots. Ensure that the suspend/resume sequence
is working fine. Ensure that the ChromeOS firmware update completes
successfully for the boot image with updated flash map and the system
boots fine after the update.

Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46569
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 15:47:14 +00:00
Wisley Chen 488bbe2c88 mb/google/dedede/var/drawcia: Add MIPI camera support
To support mipi WFC.
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM1 in devicetree

BUG=b:163879470, b:171258890, b:170936728, b:167938257
TEST=Build and boot to OS. Capture frames using camera app.

Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 15:38:23 +00:00
Angel Pons e3fd00f9e8 soc/intel/broadwell: Guard MCHBAR macro parameters
Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I6efbe70d2bb3ad776a2566365afa66afab51584e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 14:45:31 +00:00
Shelley Chen 0263e0ff65 sc7180: enable RECOVERY_MRC_CACHE
Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.

BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor.  Ensure that on first boot,
     memory training occurs and on second boot, memory training is
     skipped.

Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 06:05:22 +00:00
Xi Chen 3827f56fe1 soc/mediatek/mt8192: add dram log prefix
1 Add dram log prefix: [MEM]
2 Print error code when memtest fails.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I6c53c9cecf5996227a3e343fc703b9880d9afeac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 04:01:35 +00:00
CK Hu 3398f3152c soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 03:58:45 +00:00
Angel Pons 9190345bf0 soc/intel/xeon_sp/skx: Add missing includes
Commit 985d956 (soc/intel/xeon_sp/skx/: Clean up soc_util.c) removed
some indirect header inclusions, which resulted in a build failure.

Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46662
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 00:49:58 +00:00
Marc Jones 7a25fb8e69 soc/intel/xeon_sp: Rename cpx_generate_p_state_entries()
Prepare for common ACPI. Rename cpx_generated_p_state_entries()
to the common soc_power_states_generation() function. Add
empty soc_power_states_generation() to skx.

Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22 21:36:40 +00:00
Marc Jones 3fc04842cb soc/intel/xeon_sp/skx: Move skx specific FADT setting
Prepare for common ACPI. Move the skx specific FADT settings
from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt()
to match common/block/acpi.c.

Change-Id: I04873d13d822de514acbb58501171285bd5b020e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22 21:35:45 +00:00
Marc Jones 521a03f303 soc/intel/xeon_sp: Move uncore_inject_dsdt() call
Prepare for common ACPI code. Move uncore_inject_dsdt() to the
uncore device acpi_inject_dsdt call.

Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22 21:35:11 +00:00
Marc Jones 8066fda9ed soc/intel/xeon_sp: Move ACPI prototypes from chip.h
Prepare for common ACPI. Move the soc ACPI function prototypes from
cpx and skx chip.h to include/soc/acpi.h.

Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22 21:34:29 +00:00
Marc Jones 8972750b26 src/soc/intel/xeon_sp/skx: Update get_iiostack_info()
Add Pci64BitResourceAllocation return value to get_iiostack_info().
This matches cpx function and is used in future de-duplication.

Change-Id: I939c0101c751d9afced4ab33487958b93e59924c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 21:30:57 +00:00
Angel Pons 8f8cb95fe9 sec/intel/txt: Split MTRR setup ASM code into a macro
If necessary, SCLEAN needs to run in early romstage, where DRAM is not
working yet. In fact, that the DRAM isn't working is the reason to run
SCLEAN in the first place. Before running GETSEC, CAR needs to be torn
down, as MTRRs have to be reprogrammed to cache the BIOS ACM. Further,
running SCLEAN leaves the system in an undefined state, where the only
sane thing to do is reset the platform. Thus, invoking SCLEAN requires
specific assembly prologue and epilogue sections before and after MTRR
setup, and neither DRAM nor CAR may be relied upon for the MTRR setup.

In order to handle this without duplicating the MTRR setup code, place
it in a macro on a separate file. This needs to be a macro because the
call and return instructions rely on the stack being usable, and it is
not the case for SCLEAN. The MTRR code clobbers many registers, but no
other choice remains when the registers cannot be saved anywhere else.

Tested on Asrock B85M Pro4, BIOS ACM can still be launched.

Change-Id: I2f5e82f57b458ca1637790ddc1ddc14bba68ac49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46603
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:06:54 +00:00
Angel Pons 01490258bb sec/intel/txt: Add `enable_getsec_or_reset` function
This can be used to enable GETSEC/SMX in the IA32_FEATURE_CONTROL MSR,
and will be put to use on Haswell in subsequent commits.

Change-Id: I5a82e515c6352b6ebbc361c6a53ff528c4b6cdba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:06:26 +00:00
Angel Pons 7b4d67cf42 sec/intel/txt: Extract BIOS ACM loading into a function
Tested on Asrock B85M Pro4, still boots with TXT enabled.

Change-Id: I0b04955b341848ea8627a9c3ffd6a68cd49c3858
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:05:38 +00:00
Angel Pons 84641c8183 nb/intel/haswell: Add HASWELL_HIDE_PEG_FROM_MRC option
The MRC will perform PCI enumeration, and if it detects a VGA device in
a PEG slot, it will disable the IGD and not reserve any memory for it.
Since the memory map is locked by the time MRC finishes, the IGD can not
be enabled afterwards. Changing this behavior requires patching the MRC.

Hiding the PEG devices from MRC allows the IGD to be used even when a
dedicated graphics card is present. However, MRC will not program the
PEG AFE settings as it should, which can cause stability problems at
higher PCIe link speeds. Thus, restrict this workaround to only run when
the HASWELL_HIDE_PEG_FROM_MRC option is enabled. This allows the IGD to
be disabled and the PEG AFE settings to be programmed when a dedicated
graphics card is to be enabled, which results in increased stability.

The most ideal way to fix this problem for good is to implement native
platform init. Native init is necessary to make Nvidia Optimus usable.

Tested on Asrock B85M Pro4, using the PEG slot with a dedicated graphics
card as well as without. Graphics in both situations function properly.

Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45534
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:05:25 +00:00
Angel Pons 6c4028dd3d sec/intel/txt: Only run LockConfig for LT-SX
LockConfig only exists on Intel TXT for Servers. Check whether this is
supported using GETSEC[PARAMETERS]. This eliminates a spurious error for
Client TXT platforms such as Haswell, and is a no-op on TXT for Servers.

Change-Id: Ibb7b0eeba1489dc522d06ab27eafcaa0248b7083
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:05:01 +00:00
Angel Pons e70a3f8822 sec/intel/txt: Always run SCHECK on regular boots
When Boot Guard is disabled or not available, the IBB might not even
exist. This is the case on traditional (non-ULT) Haswell, for example.

Leave the S3 resume check as-is for now. Skylake and newer may need to
run SCHECK on resume as well, but I lack the hardware to test this on.

Change-Id: I70231f60d4d4c5bc8ee0fcbb0651896256fdd391
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:04:30 +00:00
Angel Pons 8a285fd8a5 sec/intel/txt: Allow skipping ACM NOP function
This is merely used to test whether the BIOS ACM calling code is working
properly. There's no need to do this on production platforms. Testing on
Haswell showed that running this NOP function breaks S3 resume with TXT.
Add a Kconfig bool to control whether the NOP function is to be invoked.

Change-Id: Ibf461c18a96f1add7867e1320726fadec65b7184
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:03:18 +00:00
Angel Pons c037695c19 sec/intel/txt/ramstage.c: Do not init the heap on S3 resume
It causes problems on Haswell: SINIT detects that the heap tables differ
in size, and then issues a Class Code 9, Major Error Code 1 TXT reset.

Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:02:58 +00:00
Angel Pons 8f7e2a3add sec/intel/txt/ramstage.c: Extract heap init into a function
Heap initialization is self-contained, so place it into a separate
function. Also, do it after the MSEG registers have been written, so
that all register writes are grouped together. This has no impact.

Change-Id: Id108f4cfcd2896d881d9ba267888f7ed5dd984fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:01:54 +00:00
Angel Pons 08de7d6bbd sec/intel/txt: Add and fill in BIOS Specification info
This is not critical to function, but is nice to have.

Change-Id: Ieb5f41f3e4c5644a31606434916c35542d35617a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46493
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:01:35 +00:00
Angel Pons 28d0408409 sec/intel/txt/common.c: Only log ACM error on failure
The TXT_BIOSACM_ERRORCODE register is only valid if TXT_SPAD bit 62 is
set, or if CBnT is supported and bit 61 is set. Moreover, this is only
applicable to LT-SX (i.e. platforms supporting Intel TXT for Servers).

This allows TXT to work on client platforms, where these registers are
regular scratchpads and are not necessarily written to by the BIOS ACM.

Change-Id: If047ad79f12de5e0f34227198ee742b9e2b5eb54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46492
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:00:19 +00:00
Angel Pons 5a6daa6b72 sec/intel/txt: Move DPR size to Kconfig
Instead of hardcoding the size in code, expose it as a Kconfig symbol.
This allows platform code to program the size in the MCH DPR register.

Change-Id: I9b9bcfc7ceefea6882f8133a6c3755da2e64a80c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 19:59:53 +00:00
Angel Pons 92eab64a43 configs: Add TXT-enabled config for Asrock B85M Pro4
This config selects the necessary options to enable Intel TXT on the
Asrock B85M Pro4, and allows the code to be build-tested. Note that the
current TXT code will not work, as it was written for Broadwell-DE.
Subsequent commits will adapt the code as necessary to work on Haswell.

Compatible BIOS and SINIT ACMs can be retrieved from a firmware update
for the Supermicro X10SLH. As they are not in the blobs repository, use
the STM binary as a placeholder so as to allow build-testing the code.

Change-Id: Ibf8db5fdfac5b527520023277c6370f6efa71717
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46489
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 19:59:30 +00:00
Marc Jones 985d956833 soc/intel/xeon_sp/skx/: Clean up soc_util.c
Remove unused c_util.c helper functions and clean up soc_util.h in
preparation for merging common code with cpx/.

Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 17:03:49 +00:00
Marc Jones 97321db21d soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c
De-duplicate and prepare for common ACPI. Move common
northbridge ACPI code to nb_acpi.c. There are a few
differences between the skx and cpx defined FSP hob names
and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)).

Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 16:28:16 +00:00
Marc Jones 2560ad3233 soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()
Prepare for common ACPI code. Make acpi_fill_fadt() match
intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt()
to set cpx fadt->flags.

Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 16:18:11 +00:00
Patrick Rudolph bc744f5893 drivers/smmstore: Implement SMMSTORE version 2
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.

Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
  memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
  returns error or success in registers.
* Returns an error if the requested operation would overflow the
  communication buffer.

Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.

The implementation has been tested against EDK2 master.

An example EDK2 implementation can be found here:
eb1127744a

Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22 12:29:47 +00:00
Tim Chen a693fa06cd dedede: Create metaknight variant
Create the metaknight variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:169813211
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_METAKNIGHT

Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22 12:28:25 +00:00
Shelley Chen 17df7d634d security/vboot: Remove all tpm 1.2 functions for mrc hash in the tpm
Since MRC_SAVE_HASH_IN_TPM depends on TPM2, we can now remove the tpm
1.2 versions of functions that deal with mrc hash in the tpm as it
will not be used by tpm 1.2 boards.  Also move all antirollback
functions that deal with mrc hash in the tpm under CONFIG(TPM2).

BUG=b:150502246
BRANCH=None
TEST=make sure boards are still compiling on coreboot Jenkins

Change-Id: I446dde36ce2233fc40687892da1fb515ce35b82b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-22 06:53:26 +00:00
Hung-Te Lin c47ed6e8c3 mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.

BUG=None
TEST=emerge-asurada coreboot; # also boots into emmc
BRANCH=None

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:13:43 +00:00
Nicolas Boichat 5ed4d63fe1 mb/google/asurada: enable SPI devices
Configure and initialize EC and TPM on Asurada.

BUG=none
TEST=boot asurada

Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:13:15 +00:00
Ikjoon Jang aa752158a6 soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE
BRANCH=none
BUG=b:159079785
TEST=1. Checkout https://review.trustedfirmware.org/c/4334
     2. emerge-asurada coreboot chromeos-bootimage
     3. boot asurada

Change-Id: Ieb93073beff7ec95eb5406eecbfba8192f91edce
Signed-off-by: Ikjoon Jang <ikjn@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46382
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:12:36 +00:00
Yidi Lin cbbdcb330d soc/mediatek/mt8192: Add board-specific regulator APIs
To enable DVFS, DRAM driver needs to access four different
regulators that SoC can't access directly and need board-specific
implementations.

To support that we need to define the getter and setter APIs for
those regulators.

BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I0c2d471a7f8628735af90c5b5a5ab3012831e442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46405
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:12:14 +00:00
Duncan Laurie 3502960e50 acpigen: Make acpigen_write_opregion() argument const
This structure is not modified so it can be made const and allow
the calling function to also declare it as a const structure.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:27 +00:00