Use the TSC for the Stoney Ridge monotonic timer. Modern AMD
CPUs have invariant timestamp counters. This patch brings the
feature more in line with other devices and allows the use of
typical monotonic timer functions.
BUG=chrome-os-partner:62578062
Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
- Update checkpatch.pl to version 522b837
(checkpatch: warn when formats use %Z and suggest %z)
- This update moves the const_struct definitions into an external file.
coreboot will want to update this file, but for now I'm just pulling it
in directly from the linux tree.
- Update spelling.txt used by checkpatch.pl to version 505d308
(scripts/spelling.txt: add "overide" pattern and fix typo instances)
- Add better notes where things have been changed for coreboot to make
future merges easier.
Change-Id: I0ef067874fe7b1d23276a10e63858895d6083f69
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are up to two on-board PCI devices where bus master has to be
enabled in PCI config space. As there is no need for a complete PCI
driver for these devices just set the bus master bit in
mainboard_final().
In a perfect world that would be the task of the runtime driver which
unfortunately don't do that.
Change-Id: Ic2896d5e7568a455737af26b14b2c398caae5f72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ALSB gnvs variable is used to load the OpRegion memory
address into the ASLS register on the S3 resume path, and must
therefore first be set on the normal boot path.
This patch brings Haswell in line with SNB/IVB/Nehalem, which
already save the OpRegion address in ASLB.
Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Now that pci_devs.h is part of soc/ and not used for multiple
southbridges:
* Remove devices not present in the Stoney Ridge APU
* Complete the list to include additional devices besides
those in the FCH.
BUG=chrome-os-partner:62578372
Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20370
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a memmap file with a cbmem_top() function. Remove the
LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls
to the late-only set_top_of_ram() function.
Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I9f4155285529ec28e826637a61436478f648704c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Describe RT5663 headphone codec in ACPI so it can
be enumerated by the OS.
- Supply NHLT binaries for RT5663
BUG=b:62872377
TEST=Apply full patch set and UCM, verify basic audio works.
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076
Reviewed-on: https://review.coreboot.org/20305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Problem was introduced by fb2f667da2 "nb/amd/amdk8: Link raminit_f.c"
which linked debug.c and was not tested with this option.
Change-Id: I8597a6915c65ea783a864110cb23ecb34ea0611b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the code we do the following in a number of places
to pre-initialize an array with a certain value before
overwriting some of the array with other values:
u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
}
clang does not like that behavior unless we specify
the option -Wno-initializer-overrides.
Remove the check for gcc in those places, too, because
1) it would silently change array contents between compilers
2) the check isn't sufficient to determine compilation on
clang vs gcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc
Reviewed-on: https://review.coreboot.org/20384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
clang complains that the access might be unaligned. Yes, we know. Yes,
that's exactly what we want. You have _one_ job.
Change-Id: I5400f50d8b5b462270c700f7ff90d9d517278e71
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/19659
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wow, this one is disliked by clang for the empty for() loop, but
looking at the file just makes my eyes bleed a little bit. I remember
the circumstances under which we let this code go in. It was supposed
to save contributions from a vendor, but that never worked out.
Just to keep the little chunks down, here's an indent run and some of
the cruft removed that doesn't actually contribute to functionality in
any way.
Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix CID 1376472 detected by coverity. Zero extend the capacity instead
of sign extending it.
TEST=Build and run on reef
Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
That seems to be the more reliable way to build clang cross compilers
for now.
Change-Id: I14fe767d20f91b64e96c909291760bddcd108e5c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/19660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a SMM_TSEG_SIZE symbol that can be used in top of memory
calculations.
Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove IDE from the Stoney Ridge source. This APU doesn't have
an IDE controller. The support was left over from pi/hudson.
BUG=chrome-os-partner:62580062
Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the pcie.c file. Historically PCIe lanes have been
available from the Gfx and/or the FCH. The integrated FCH in
this APU has no PCIe available.
BUG=chrome-os-partner:62580062
Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs. Remove this support from the source.
This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c.
BUG=chrome-os-partner:62580062
Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the majority of reported errors and mark most of the
remaining ones as todo. Some of the lines requiring a >80
break are indented too much currently.
Changes to agesawrapper.c cause the build to change, so this
file is also left as-is. Make hex values consistently lower-case.
BUG=chrome-os-partner:622407746
Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.
BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.
Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
- Excludes certain phrases which can't be changed.
- Checks last commit message if code is in a repo.
Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20032
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the checkpatch errors reported in the asl files and
make other stylistic modifications.
These changes were confirmed to cause no changes in a Gardenia
build.
BUG=chrome-os-partner:622407746
Change-Id: Id8b2620d161062c444e493325d83bb158705b76b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I0a024d82d331c0794fe087e440b4e1924129a13c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Don't ask for bootstrapping in case of a different host GCC major
version. GCC's versioning scheme changed starting with the release
of GCC 5. There are no big changes between the versions any more.
Instead, show the message when the host GCC's version is below 4.
In case GNAT can't be found, ask the user to abort and install it.
Also give hints for Ubuntu where the package versions are a little
messy (e.g. the meta packages gcc and gnat often point to different
versions).
In case GNAT is found but is too old (< 4.9), enable bootstrapping
by default and tell the user that building will take longer.
In all three cases show a timeout to draw the user's attention.
v2: Update GNAT check to also look for `gnatbind`. It has to be
somewhere in $PATH.
Change-Id: I4d9de11d7469e137ede8ad138296d20c0f8ba78f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20332
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
"quit" is a signal name. The FreeBSD `sh` interprets
trap quit 1 2 3 15
as command to reset all the respective signal handlers, instead
of setting quit() as handler.
Change-Id: I69b813ab583f15a9dd89a115f7aea66d966f981b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20391
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.
Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When using the regular `if` construct, the compiler will check
the guarded code independently from the condition.
Change-Id: I00c5c7ae3720f75aa9415edb94cd2ce76cee8aee
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
... even though the author of the code probably wished he was
working on a (much faster) broadwell system instead. Let's fix
the header guard to reflect the right SOC.
Noteworthy: clang detected that this was wrong.
Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Lijian Zhao