TEST=Resulting image of timeless build for Mandolin doesn't change.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44cb7759206e9e1ce79fd57f62b9a844e52f7394
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72857
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all family
15h model 60h and 70h steppings.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id05f849d59c04efa9f38dd66892f3cb99d94e3ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72855
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are multiple Phoenix steppings, but that is now covered by using
CPUID_ALL_STEPPINGS_MASK.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4eb3502dec5ebdfdbba263b15b34621952d0554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Glinda
steppings once GLINDA_A0_CPUID is updated.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9b8cbb2dc925a8258db6a4eb0d1b00b2745637f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72852
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all
Phoenix 2 steppings that might be available in the future. Right now it
shouldn't change any behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If9878b4687360250cac4cfe1409d5dbad7147cf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72851
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all
Mendocino steppings that might be available in the future. Right now it
shouldn't change any behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77ea8c6162667e0a318176e62078b1f57726c10c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72850
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CPUID_ALL_STEPPINGS_MASK as CPUID match mask to support all Cezanne
steppings. This adds support for Cezanne stepping A1 and possible future
steppings.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb020052685d9369109f391797fdd8f8790a91d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72849
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CPUID_ALL_STEPPINGS_MASK to only need one CPU device ID table entry
per family & model combination and not one per stepping.
TEST=Mandolin with a Picasso APU with PICASSO_B1_CPUID (0x00810f81)
still finished mpinit and boots successfully even though now only
PICASSO_B0_CPUID (0x00810f80) with CPUID_ALL_STEPPINGS_MASK specified as
device match mask. When commenting out the line with PICASSO_B0_CPUID
as a negative test, mpinit fails as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00ba43834ad86ecffa09d60599b17d122acd0b99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72848
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of always doing exact matches between the CPUID read in
identify_cpu and the device entries of the CPU device ID table,
offer the possibility to use a bit mask in the CPUID matching. This
allows covering all steppings of a CPU family/model with one entry and
avoids that case of a missing new stepping causing the CPUs not being
properly initialized.
Some of the CPU device ID tables can now be deduplicated using the
CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this
patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0540b514ca42591c0d3468307a82b5612585f614
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Both Alder Lake and Tiger Lake have Kconfig options for S3, which
disables support for D3Cold. Unify these so that they are easier
to compare.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since all SoCs define the df_mmio_control union for the bits used in the
code, data_fabric_print_mmio_conf can take advantage of that and also
print a decoded version of those bits.
Output on Mandolin before the patch:
=== Data Fabric MMIO configuration registers ===
idx control base limit
0 93 fc000000 febfffff
1 93 10000000000 ffffffffffff
2 93 d0000000 f7ffffff
3 1093 fed00000 fedfffff
4 90 0 ffff
5 90 0 ffff
6 90 0 ffff
7 90 0 ffff
Output on Mandolin with the patch:
=== Data Fabric MMIO configuration registers ===
idx base limit control R W NP F-ID
0 fc000000 febfffff 93 x x 9
1 10000000000 ffffffffffff 93 x x 9
2 d0000000 f7ffffff 93 x x 9
3 fed00000 fedfffff 1093 x x x 9
4 0 ffff 90 9
5 0 ffff 90 9
6 0 ffff 90 9
7 0 ffff 90 9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06e1d3a3e9abd664f59f2bb852394e7f723f2b30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
In contrast to Mendocino and all other AMD SoCs in the coreboot tree,
Rembrandt, on which Mendocino is based on, has a DF_MMIO_REG_SET_SIZE of
3 instead of 4, so the next data fabric MMIO register is 3 DWORDs after
the last one instead of the 4 DWORDs on the other SoCs. This was checked
against PPR #56558 Rev 3.04.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I454ad5d182f0040db93c9b3a83941333392c6061
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
To be able to handle a special case, add a per-SoC define for
DF_MMIO_REG_SET_SIZE instead of having this hard-coded as 4 in the
DF_MMIO_* macros. To avoid some duplication, also introduce the
DF_MMIO_REG_OFFSET macro.
TEST=Output from data_fabric_print_mmio_conf doesn't change on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67420a2973c8ef9a7f0ce19ddc0013de69731689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since the MMIO decode range registers in the data fabric are part of the
data fabric and not of the northbridge, replace the NB prefix with a DF
prefix to make this a bit clearer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ife5e4581752825e9224b50252955d485a067af74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This should make it a bit clearer that those registers are in the data
fabric configuration registers. Also move those defines right after the
register definition those are related to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
CPUID 0x00a70f80 is Phoenix 2 and not Phoenix, so update the define name
to match.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7500130d5470fdd824980b81746f3a0f6d277d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72843
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Since things are done a bit differently on Stoneyridge, it's probably
safer to run a test instead of assuming that the test on Picasso was
sufficient to be reasonably sure that this will also work as expected on
Stoneyridge.
TEST=No change of ACPI-related messages in dmesg with this patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I432752fae8be08d3cbd7d30215b350c4528c7206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Instead of just printing the register contents, normalize the contents
of the base and limit registers to actual MMIO addresses and then print
those. This will hopefully avoid some confusion caused by the shifted
addresses.
Output on Mandolin before the patch:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 93 fc00 febf
1 93 1000000 ffffffff
2 93 d000 f7ff
3 1093 fed0 fedf
4 90 0 0
5 90 0 0
6 90 0 0
7 90 0 0
Output on Mandolin after the patch:
=== Data Fabric MMIO configuration registers ===
idx control base limit
0 93 fc000000 febfffff
1 93 10000000000 ffffffffffff
2 93 d0000000 f7ffffff
3 1093 fed00000 fedfffff
4 90 0 ffff
5 90 0 ffff
6 90 0 ffff
7 90 0 ffff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.
Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21. This will
change the value on some platforms.
Any conflicts should get sorted out later in the conversion process.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Glinda SoC, remove it form the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I627d05c09d9637caf15e17285dd2c8e0389747c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Phoenix SoC, remove it form the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Mendocino SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Cezanne SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Picasso SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Stoneyridge SoC, remove it form the global
NVS and add an ACPI object for this in the DSDT of the mainboards that
use it in their ACPI code. Eventually the LIDS object should probably be
moved to the EC's ACPI code, but that's out of scope for this patch.
TEST=google/liara doesn't show ACPI errors in Linux' dmesg
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This simplifies the code flow of the cpu init. APL can do CPU init after
calling FSP-S, while GLK needs to do that before. This is now reflected
directly in the cpu ops rather than using
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT as a proxy.
Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Not exactly sure about the usb4_xhci controllers, but for now I assume
those will behave like any other XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22384f58e245a1486793831d29d22e9c618f646c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and
PPR #57396 Rev 1.54 were used as a reference. Some devices will need to
have ops added in future patches. Since the xhci_2 device isn't there
any more, also drop it from the mainboard devicetrees. The actual USB
port configuration on xhci_0 and xhci_1 is updated in the next patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Now that the PCIe ports on device 1 are added, rename the aliases for
the PCIe ports on device 2 to have a common naming scheme. For phoenix
the device alias names are based on the device and function number the
bridge is connected to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only the PCIe ports on the functions of device 2 were present in the
devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the
missing PCIe ports on the functions of device 1 and assign the
amd_external_pcie_gpp_ops ops to them.
This SoC uses a slightly different naming scheme for its PCIe GPP ports.
Previously the PCIe GPP bridge number from the PCI Device ID Assignments
table from the PPR was used. Those bridge numbers are one less than the
function numbers of the device. This is due to function 0 being a dummy
bridge to avoid having to shuffle around the function numbers when the
first bridge is unused, since the PCIe specification mandates the
function 0 to be implemented if any other function on the same device is
implemented. In order for the device aliases to be consistent with the
PCIe device and function numbers which is way more commonly used and
also what lspci shows and what goes into the DXIO descriptors, change
the naming scheme of the aliases.
This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch requests FSP to enable the MRC fast boot feature along
with FSP v2473.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4a621e55c853505f7a702181ae5a70dc56d5b5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72745
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit b171f76812 ("soc/amd/*: Hook up GPP bridges ops to devicetree")
missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge
PCIe ports, so add them. Those devices were previously covered by the
PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that
got removed in the referenced commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55434bf486569b32901b3840193a09cc5955abb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This switches the Picasso SoC to use the common reset code.
Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET
flag.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This switches the Phoenix & Glinda SoCs to use the common reset code.
Cezanne and newer do not support warm reset, so use cold resets in all
cases (including the OS).
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This switches the Cezanne & Mendocino SoCs to use the common reset code.
This patch does not change any behavior on those chips.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda.
PCO supports the warm reset, and future chips can support it by setting
the SOC_AMD_SUPPORTS_WARM_RESET option.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No bootstate hook is called on exit of BS_OS_RESUME or BS_PAYLOAD_BOOT.
Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit provides a dev tree setting for partners to enable/disable
TccoldHandshake for the sighting in doc:723158
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=compile ok and FSP UPD is config properly
Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68635
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some reserved address range listed in Alder Lake Platform Firmware
Architecture Specification document 626540 section 6.4 ADL - System
Memory Map such as North TraceHub ranges were missing. Details about
North TraceHub (aka. Intel TraceHub) can be found in Intel Trace
Hub (Intel TH) Developer's Manual document 671536.
BUG=b:264648959
TEST=Compilation successful
Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch adds the {MCH:a706, TDP:28W} missing 28W configuration.
BUG=b:267666609
BRANCH=firmware-brya-14505.B
TEST=Power Limit are properly set on skolas 28W
Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
If we show the user early signs of life during CSE FW sync or MRC
(re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL).
These can be used to ensure persistence across global reset (e.g. after
CSE sync) so that they can be later retrieved in order to build things
such as test automation ensuring that we went through the SOL
path/display initialized.
BUG=b:264648959
TEST=event shows in eventlog after CSE sync and/or MRC
Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2
Signed-off-by: Tarun Tuli <taruntuli@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
USB1_DRV_VBUS is used to provide 5V power for USB on MT8188 EVB and it's
not used on Geralt. Therefore, remove the GPIO setting of USB1_DRV_VBUS.
TEST=read usb data successfully.
BUG=b:236331724
Change-Id: Iffea7b288c83c81648d4c7ca30d2f0961f9853ff
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72641
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With New Crypto upgrade we need to have 1 block of 4Kb increase in
romstage, by which we can see an improvement of Boot performance
by 100 msec.
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board
Boot performance improved by 100 msec observed.
Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
During boot, gpi_firmware_load gets called twice because there are
2 serial engines. Thus gsi_fw blob is also decompressed twice and is
written to base addresses of SEs. This is redundant.
Perform the decompression once on first call and save the header
in static variable which can be reused in next call.
BUG=b:262426214
TEST=Validated on qualcomm sc7280 development board
Saving of 80ms observed while testing with 130 boot cycles.
Change-Id: If98a3974f0791dffdf675c02cc28375d0485c485
Signed-off-by: Vijaya Nivarthi <vnivarth@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71927
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
