Haswell does not use reg-script, but does more or less the same thing.
Adapt Broadwell to ease the eventual unification with Haswell.
Change-Id: I4d3e0d235b681e34ed20240a41429f75a3b7cf04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove all typedefs and cleanup references to all structs and enums.
BUG=b:159061802
TEST=Boot morphius to shell.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.
BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor. Ensure that on first boot,
memory training occurs and on second boot, memory training is
skipped.
Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 985d956 (soc/intel/xeon_sp/skx/: Clean up soc_util.c) removed
some indirect header inclusions, which resulted in a build failure.
Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46662
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prepare for common ACPI. Rename cpx_generated_p_state_entries()
to the common soc_power_states_generation() function. Add
empty soc_power_states_generation() to skx.
Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Prepare for common ACPI. Move the skx specific FADT settings
from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt()
to match common/block/acpi.c.
Change-Id: I04873d13d822de514acbb58501171285bd5b020e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Prepare for common ACPI code. Move uncore_inject_dsdt() to the
uncore device acpi_inject_dsdt call.
Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Prepare for common ACPI. Move the soc ACPI function prototypes from
cpx and skx chip.h to include/soc/acpi.h.
Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add Pci64BitResourceAllocation return value to get_iiostack_info().
This matches cpx function and is used in future de-duplication.
Change-Id: I939c0101c751d9afced4ab33487958b93e59924c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove unused c_util.c helper functions and clean up soc_util.h in
preparation for merging common code with cpx/.
Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
De-duplicate and prepare for common ACPI. Move common
northbridge ACPI code to nb_acpi.c. There are a few
differences between the skx and cpx defined FSP hob names
and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)).
Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Prepare for common ACPI code. Make acpi_fill_fadt() match
intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt()
to set cpx fadt->flags.
Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To enable DVFS, DRAM driver needs to access four different
regulators that SoC can't access directly and need board-specific
implementations.
To support that we need to define the getter and setter APIs for
those regulators.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I0c2d471a7f8628735af90c5b5a5ab3012831e442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46405
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This driver is for the root port device and needs to reference the
parent device for its ACPI scope. Similarly for the debug output it
needs to use the parent device, and fall back to the chip name if
config->desc is not provided in the devicetree.
The UID property is removed. This value is not the same as the port
number; according to some docs it should be unique but it is not fully
clear what it should be tied to. Regardless, it is not used by the
Thunderbolt driver in the kernel.
I also renamed some functions/structures to be clear that this is just
an ACPI driver for the PCIe root port and not a driver for the root port
itself. As part of this I removed the PCI based resource operations and
the scan bus function since this device does not have children itself.
Finally I added a detailed comment with an example describing what the
driver is for and what properties it generates.
TEST=boot on volteer and ensure the USB4 root port device and properties
are added to the SSDT as described by the comment in chip.h.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The USB4 host interface (DMA) devices need to use SA_DEVFN_*
instead of SA_DEV_* when determining the ACPI name.
The matching names are removed from the SOC-level ACPI name
handler since they are provided by this driver now.
TEST=boot on volteer and ensure TDM0 device is in the SSDT.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: If778bda82b80593452a590962dbffef6eff6484a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.
Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This converts the constant for the XTAL frequency to a Kconfig option.
Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and
select it by the appropriate SoCs.
This Kconfig gets used in the follow-up changes.
Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Picasso build describes the DRAM region where the PSP places
our bootblock. Rather than relying on Kconfig values, make the build
more robust by using the actual size and target base address
from the boot block's ELF file.
Sample output of "readelf -l bootblock.elf" is:
------------------
Elf file type is EXEC (Executable file)
Entry point 0x203fff0
There is 1 program header, starting at offset 52
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .data .bss .reset
------------------
We can extract the information from here.
BUG=b:154957411
TEST=Build & boot on mandolin
Change-Id: I5a26047726f897c57325387cb304fddbc73f6504
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load params from flash and use those params to do dram fast calibration.
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of
AES-NI enablement as precaution, as suggested in Intel document
325384-070US.
Locking is enabled by default (as already done in SKL and Arrandale) and
may be disabled by the newly introduced Kconfig in the parent change.
Tested by checking the MSR.
Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The PSP does not accept the SmmInfo command during a resume so
remove the call.
BUG=b:163017485
TEST=Run SST on trembyle, verify error message goes away
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the base address. This should have no noticeable effect,
as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The
argument writes were not getting to any target.
BUG=b:171037051
TEST=Run SST on morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The XTAL shutdown (dis)qualification bit already unconditionally gets
set to 1 by FSP for these platforms, making this code redundant.
Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The subsystem ID registers are read/write-once. Writes by coreboot will
not take effect if FSP sets them.
Note that FSP sets one device ID for the SA devices and another for PCH
devices. coreboot will copy individual vendor and device IDs if
subsystem is not provided.
Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects source memory is overrun. Fix this issue by using
the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption.
Found-by: Coverity CID 1429762 1429774
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp.
Instead of using hardware acceleration for whole RSA process,
acclerating only calculation part(modexp) increases transparency
without affecting boot time.
BUG=b:169157796
BRANCH=zork
TEST=build and flash, check time spent on RSA is not changed
Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
platform_fsp_silicon_init_params_cb is called by the fsp driver and
calls mainboard_silicon_init_params which sets the mainboard
PCH GPIOs.
Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the Kconfig for hyperthreading to be always able to check at
runtime if hyperthreading is supported. Having a Kconfig for this
doesn't have any benefit.
Change-Id: Ib7b7a437d758f7fe4a09738db1eab8189290b288
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to platform-specific constraints, it is not possible to enable DPR
by programming the MCH's DPR register in ramstage. Instead, assume it
has been programmed earlier and check that its value is valid. If it is,
then simply configure DPR in TXT public base with the same parameters.
Note that some bits only exist on MCH DPR, and thus need to be cleared.
Implement this function on most client platforms. For Skylake and newer,
place it in common System Agent code. Also implement it for Haswell, for
which the rest of Intel TXT support will be added in subsequent commits.
Do not error out if DPR is larger than expected. On some platforms, such
as Haswell, MRC decides the size of DPR, and cannot be changed easily.
Reimplementing MRC is easier than working around its limitations anyway.
Change-Id: I391383fb03bd6636063964ff249c75028e0644cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds some Kconfig hints to make it clearer that the
USE_QC_BLOBS option is required for SC7180 boards and guide the user in
the right direction through menuconfig. Also add those little arrows to
the Trogdor board options that are there on most other boards.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
msr_set_bit can only set single bits in MSRs and causes mixing of bit
positions and bitmasks in the MSR header files. Thus, replace the helper
by versions which can unset and set whole MSR bitmasks, just like the
"and-or"-helper, but in the way commit 64a6b6c was done (inversion done
in the helper). This helps keeping the MSR macros unified in bitmask
style.
In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get
added.
The few uses of msr_set_bit have been replaced by the new version, while
the used macros have been converted accordingly.
Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configuration option shares a name with the FSP UPD, but
is enumerated differently. Change its name to minimise confusion
about the options.
Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Prepare for common ACPI. Add get_system_memory_map() helper
function to soc_util.c and use it in the SRAT ACPI code
to match the cpx code.
Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.
Tested on an Acer Aspire VN7-572G (Skylake-U).
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This comment does not follow any of the styles outlined in the coding
style page of the documentation. Adjust it to match the preferred style.
Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
