Commit Graph

22487 Commits

Author SHA1 Message Date
Lijian Zhao 6fbf98a462 intel/fsp: Update cannonlake FSP header
Update FSP header file to latest version, cannonlake reference code 
7.0.14.11. Details of FSP changes can be find in FSP release notes.

Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04 02:55:29 +00:00
Arthur Heymans 74bd2b0e4c mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBOND
The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already
includes this.

Change-Id: Ib2de0f384a547240528b18f07327566354164699
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-04 02:53:31 +00:00
Kyösti Mälkki 7334c6f868 soc/amd/stoneyridge: Drop some amdlib.h includes
Change-Id: Ief00a74a9ab4cb6783ea17cebc924b5c4852f228
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-04 02:47:25 +00:00
Jonathan Neuschäfer 92d483a892 buildgcc: Implement simple tarball hash verification
This patch implements a relatively simple hash-based verification scheme
for downloaded files (tarballs):

After buildgcc downloads a file or notices that it has already been
downloaded, it hashes the file, and compares the hash against the known
hash stored in util/crossgcc/sum/$filename.cksum. Two errors can occur:

1. The hash file is missing. In this case, crossgcc asks the user to
   verify the authenticity of the downloaded file. It also calculates
   its hash and stores it in util/crossgcc/sum/$filename.cksum.calc.
   If the file is authentic, the user may rename the calculated hash
   file to $filename.cksum, so that it can be found the next time
   buildgcc is started.

2. The known hash and the calculated hash differ. This is the case that
   this patch seeks to protect against, because it may imply that the
   downloaded file was unexpectedly changed, either in transit
   (Man-in-the-Middle attack) or on the file server that it was
   downloaded from. If buildgcc detects such a hash mismatch, it asks
   the user to delete the downloaded file and retry, because it can also
   be caused by a benign network error. If, however, the error persists,
   buildgcc can't continue without risking that the user runs malicious
   code, and it stops.

Note: The hash algorithm may be changed in the future, but for now I
left it at SHA-1, to avoid bloating this patch.

Change-Id: I0d5d67b34684d02011a845d00f6f5b6769f43b4f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-10-04 02:43:02 +00:00
Bora Guvendik b632c29aeb soc/intel/cannonlake: change gpio device name
TEST=Boot to OS

Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21758
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:51:19 +00:00
Rajneesh Bhardwaj 868b3761c7 mainboard/google/soraka: Reduce Wacom resume time
Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.

BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.

Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-03 20:25:39 +00:00
Lijian Zhao ed3e6b8b94 soc/intel/cannonlake: Disable CPU ratio override
Disable CPU Ratio override as input to FSP Memory init.

Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:24:42 +00:00
Bora Guvendik 5d11cc9d7e soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
Add ACPI methods for gpio, scs and pcr.

TEST=Boot to OS.

Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-03 20:24:35 +00:00
Lijian Zhao 747f05675e soc/intel/cannonlake: Add northbridge dsdt table
Add ACPI dsdt table for northbridge, report proper resources in dsdt
entries.

TEST=Boot up into OS fine.

Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:24:08 +00:00
Lijian Zhao c1a4928609 mainboard/intel/cannonlake_rvp: Add smi support in board
Include SMI Handler support for Cannonlake RVP platform.


Change-Id: I8f363e20a6eb92b3c05e16715aa052a8da18b509
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:23:47 +00:00
Lijian Zhao f0eb99996d soc/intel/cannonlake: Fill the SMI usage
Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.

Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:23:41 +00:00
Lijian Zhao a515849259 soc/intel/cannonlake: Add lpc pci driver
1.Add common ITSS support as part of LPC driver init code.
2.Add LPC pci driver for CNL

Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:23:32 +00:00
Ravi Sarawadi 1483d1fcda soc/intel/skylake: Enable common LPC IP
Enable Skylake to use the new common LPC code. This
will help to reduce code duplication and streamline code bring up.

Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:23:21 +00:00
Ravi Sarawadi a9b5a39395 soc/intel/common/block: Update LPC lib
Add support for following functionality:
 1. Set up PCH LPC interrupt routing.
 2. Set up generic IO decoder range settings.
 3. Enable CLKRUN_EN for power gating LPC.

Change-Id: Ib9359765f7293210044b411db49163df0418070a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 20:22:58 +00:00
Martin Roth 51bfc594bb vc/amd/pi/00670F00: Remove HeapXXBuffer functions
The HeapAllocateBuffer and HEAPDeallocateBuffer functions are not used
in Stoney Ridge, so get rid of them.

Change-Id: I716d5c8957ced52c25fd501697111b1b0b263467
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-03 20:18:18 +00:00
Martin Roth 6d8ef24566 soc/amd/stoney: Allow alternative placement for AMD FW directory
Allow the AMD FW directory to be placed at one of the alternative
locations within the ROM.

BUG=b:65484600
TEST=Assign PSP firmware location, build & test.

Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03 20:15:17 +00:00
Nico Huber ca3e121607 nb/intel/gm45: Remove UMA alignment optimization
This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.

TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.

Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-03 19:48:01 +00:00
Marc Jones 29922a5409 soc/amd/stoneyridge: Wait for UART to be ready
The Stoney Ridge UART and AMBA devices must be powered and report power
and clock OK prior to using the coreboot serial console. The code used
to have a delay to wait for the power and clock, but didn't check the
OK bits. This caused long delays on a reboot, as each byte would time out
until the console was reset again at romstage.

This change also removes the UART reset. The device has just been
powered and is in reset already. Testing indicates the reset isn't
needed.

BUG=b:65853981
TEST=Boot to Chrome OS, run the reboot command, verify that the long
delay is gone.

Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-03 17:56:37 +00:00
Martin Roth 4460e8fc56 vendorcode/amd/pi: Put libagesa build all in libagesa directory
Half the files were being placed in build/agesa and half in
build/libagesa.

Change-Id: Ied69dafffe2eb3354bd430789e098a1cb1d40551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-03 15:28:55 +00:00
Nico Huber ac4f21631b nb/intel/sandybridge: Refactor dram_dimm_mapping()
Remove no-op statements and code-rephrasing comments, apply some cosmetic
changes to improve readability.

Change-Id: I124a6bc338c2589fab66ca91bf53139b4413d10b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-03 12:37:23 +00:00
Kyösti Mälkki f824784a20 binaryPI: Fix boot regressions
Fix boot regression after commit

  d4955f0 AGESA: Move API interface under drivers/

Boards were left without cache-as-ram setup code
and appeared completely dead.

Change-Id: I53a58b817310e91566db3fd660a2c41556f3df5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2017-10-02 23:40:38 +00:00
Marshall Dawson 4dd2269f57 amd/stoneyridge: Remove 16MB cbmem assert
Do not check for the top of memory being 16MB-aligned near the end of
romstage.  This is not the expected alignment using the default 8MB SMM
region size.

BUG=b:67320715

Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:35:10 +00:00
Shaunak Saha 25cc76ff48 soc/intel/common/block: Move power button SMI functions to common PMC block
This patch moves the functions update_pm1_enable and read_pm1_enable
to common block PMC. We rename the functions to pmc_update_pm1_enable and
pmc_read_pm1_enable to keep semantics consistent.

Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-02 22:32:51 +00:00
Hannah Williams 1760cd3eb4 soc/intel/skylake: Use common/block/gpio
Other than switch to use common gpio implementation for skylake based
platform, also apply the needed changes for purism board.

Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 22:32:33 +00:00
Marshall Dawson a05fdcb269 amd/stoneyridge: Change SMM setup functions
Remove the APMC-specific initialization call.  Make the function
which programs the event type not static and call it from the
southbridge.c file.

Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:31:32 +00:00
Marshall Dawson f039a0befc amd/stoneyridge: Add PM defintions to southbridge.h
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:31:14 +00:00
Marshall Dawson 36a2356fb1 amd/stoneyridge: Refactor SMI handler
Rewrite the handler to be more compact and extendable.  The old
functionality is duplicated after the rewrite.  All SMI source registers
(except for SmiSciStatus) behave identically so these are consolidated.
Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on.

Create a table of mini-handlers to be supported in the soc directory.
As SMI sources are discovered, attempt to find the corresponding handler
and then execute it.

Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:30:57 +00:00
Marshall Dawson c6c4a213c5 amd/stoneyridge: Clean up smihandler.c
Replace hardcoded values with defined ones.

Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:30:20 +00:00
Marshall Dawson 66e62da4c7 amd/stoneyridge: Check SMI command address before reading
Use the currently programmed address of the SMI command port before
checking the passed command.  This ensures we're reading the right
port in case the port was relocated without our knowledge.

Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 22:30:02 +00:00
Marshall Dawson eecb794c96 amd/stoneyridge: Move pm/smi_read/write functions to util file
Pull all pm_read and write, smi_read and write variants into a single
file.

Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:27:38 +00:00
Marshall Dawson 16745e39b6 amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge
Duplicate existing pm_read and pm_write and create 32-bit register
access functions.

Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:27:19 +00:00
Marshall Dawson f7ace0da45 amd/stoneyridge: Fix pm_read16 argument size
Make pm_read16() consistent with the other PM register access functions.

Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:27:00 +00:00
Marshall Dawson 9db0a2dcc8 amd/stoneyridge: Clean up smi_util.c
Replace hardcoded values with defined ones.

Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:26:50 +00:00
Marshall Dawson 714c087788 amd/stoneyridge: Add more SMM definitions
Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:26:38 +00:00
Marshall Dawson abac64d4d0 amd/stoneyridge: Add uart.c to smm-y list
This corrects a build error when a developer needs DEBUG_SMM and one
of the APU's internal UARTs is used.

Change-Id: Ie1962e969a8cb93eefc0b86bf4062752580e5acd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02 22:26:05 +00:00
Julius Werner e0459c78e4 google/gru: Fix pmu1833_volsel handling
RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V
or 3.0V. We thought this mechanism was disabled by default, but it turns
out it wasn't. We want to use that pin as an output GPIO on Scarlet so
we need to reconfigure the respective SoC controls before we do that. It
seems that we also need to explicitly pinmux the pin away from that
special function (to normal GPIO) or weird things happen on some boards.

BUG=b:66534913
TEST=Sprinkled several long udelays, poked test points with a
multi-meter on Scarlet.

Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-02 18:32:11 +00:00
Aaron Durbin cf20c90430 util/cbmem: fix feedback for 'be explicit about memory map sizes'
Julius made some suggestions to fix/improve commit 46300aa2.
Implement those.

BUG=b:66681446

Change-Id: I6becac9ffdcc65745e88734dfb80d12b581584a1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-02 17:16:14 +00:00
Martin Roth 7c48b891fe mainboard/amd: Add required callouts to Stoney BiosCallouts.c
Hook the new required AGESA callout functions into the callouts tables.

BUG=b:66690176
TEST=Build and boot Kahlee - see the functions get called.

Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:24:53 +00:00
Martin Roth f80a431c11 soc/amd/common: Add framework for missing AGESA callouts
These are required callout functions that currently are not implemented.
agesa_LateRunApTask does not seem to be called, but the others are.

BUG=b:66690176
TEST=Build Kahlee.  Tested in next commit.

Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21707
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:24:49 +00:00
Shelley Chen da6e4f6935 google/fizz: Enable wake-on-usb attach/detach
BUG=b:62095784, b:35775024
BRANCH=None
TEST=Run powerd_dbus_suspend from kernel.  Plug in
     usb device and make sure wakes up.

Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:20:31 +00:00
Marshall Dawson df31904133 cpu/x86: Align stack in SIPI handler
Ensure the stack is properly aligned in the SIPI handler.  This
avoids an exception when an aligned instruction is performed on
stack data.

BUG=b:66003093
TEST=boot kahlee built with gcc 6.3

Change-Id: Ibdd8242494c6a2bc0c6ead7ac98be55149219d7c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02 16:15:42 +00:00
Richard Spiegel 38f19400f9 soc/amd/stoneyridge/southbridge.c: Remove preprocessor #if
Replace #if and #endif with runtime <if (condition) {> and <}>

Code Files: southbridge.c
BUG=b:62200891

Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-02 16:08:17 +00:00
Marshall Dawson e9b862eb2c amd/stoneyridge: Use generic SMM command port values
Remove the old Hudson-specific SMM command port definitions and use the
ones in cpu/x86/smm.h.

Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30 20:34:28 +00:00
Marshall Dawson 6746d3784f amd/stoneyridge: Remove HAVE_SMI_HANDLER from makefile
Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless
to use the variable in Makefile.inc.  Make all files built into smm
unconditional.

Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30 20:32:48 +00:00
Marshall Dawson b639bef836 soc/amd/common: Add included directory
If the symbol SOC_AMD_COMMON is selected, include the soc/amd/common
directory.  Until now this has been working due to the directory being
included as part of AGESA_INC in vendorcode.  That one is still
necessary in order to build the AGESA code so it is left in place
for now.

Change-Id: Ia8191897d2030c475c9268ae86faaf01952c6ace
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30 20:29:11 +00:00
Patrick Rudolph c060fb5aac soc/intel/braswell/acpi: Clean OpRegion up
Reorder code and put platform specific bits into update_igd_opregion.
Get rid of get_fsp_vbt and init_igd_opregion.
Write GMA opregion in case a VBT was provided, even when no FSP_GOP
is to be run.
Use SOC_INTEL_COMMON_GFX_OPREGION to reduce code duplication.

Change-Id: Ibabeb05a9d3d776b73f6885dcca846d5001116e7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-30 01:24:47 +00:00
Kyösti Mälkki 7c60498de7 AGESA binaryPI: Drop amdlib.h in BiosCallouts.c
Some fam14 boards will need more work on this area,
those are to be addressed with followup patches.

Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-29 05:46:19 +00:00
Kyösti Mälkki 8e2f6caaf0 AGESA binaryPI: Drop amdlib.h in dimmSpd.h
Change-Id: Ic1713d1530071e29bd04b525f68d4a44d20ea2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-29 05:45:53 +00:00
Kyösti Mälkki 4286502140 AGESA binaryPI: Fix indirect AGESA.h include
Change-Id: I5e2affe337f7e61ca79530b3a77af963e8692ff1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-29 05:45:44 +00:00
Nick Vaccaro d3e00ab209 google/zoombini: Add new board
Add zoombini board files using cannonlake and FSP 2.0.
Copied most initial files from poppy and cannonlake_rvp.

BUG=b:64395641
BRANCH=None
TEST=Compiles successfully using "./util/abuild/abuild
-p none -t google/zoombini -x -a"

Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-28 18:28:59 +00:00