RAM_ID GPIOs are configured by ABL based on the information added to
APCB. coreboot does not need to configure these pads. This change
drops the RAM_ID configuration from trembyle baseboard. Dalboz never
really configured RAM_IDs in coreboot.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1dfcc3c185304d917ab4386920445ba0119ac69
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252710
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the GPIOs that need to be configured for early
access in coreboot to early_gpio_table[] in
gpio_baseboard_common.c. These GPIOs include:
* Pads to talk to EC
* Pads to talk to TPM
* Pads to talk to serial console
These should be configured in the first stage that runs coreboot
i.e. in case of VBOOT_STARTS_BEFORE_BOOTBLOCK, it should be done as
part of verstage (which starts on PSP), else it should be done as part
of bootblock (which is the first stage that runs on x86).
This change drops GPIO_137 from early_gpio_table since that is not
really required in early stages.
BUG=b:154351731
TEST=Verified that trembyle still boots.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbdbb02cbfc65ddb68f0ae75cf4b1f2ea1656b91
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252709
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
`commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42716
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The host bridge's resources covering bus numbers assumed
256 buses were being decoded. However, MMCONFIG was only
covering 64 buses. This results in Linux complaining:
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000
[bus 00-3f] only partially covers this bridge
When retrieving the host bridge's resources fix up the
bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't
keep IASL from complaining when trying to do this statically.
BUG=b:158874061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add UPD xhci0_force_gen1 for Trembyle and Ezkinil.
The default setting is set to disable, and set enabled for Ezkinil.
Trambyle -> set default as disable.
Ezkinil -> set enable by request.
BUG=b:156314787
BRANCH=trembyle-bringup
TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle.
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1) Based on malefor schematics, disable unused I2C port, USB port, TBT
PCIe
2) Add audio device to the tree
BUG=b:150653745, b:154973095
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Boot to kernel and check the devices' function worked properly.
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the volteer2 variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
Modified to alphabetize and update to duplicate latest volteer changes
currently in the review and merge pipeline.
Added the following missing files from the variants/volteer2/ folder:
- gpio.c
- include/variant/acpi/dptf.asl
- acpi/mipi_camera.asl
- Makefile.inc
- memory/dram_id.generated.txt
- memory/Makefile.inc
- memory/mem_list_variant.txt
- overridetree.cb
BUG=b:159135047
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLTEER2
Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after
booting to kernel. Fix the error by properly creating the buffer field
CDW1 to cover all errors scenarios.
BUG=b:140645231
TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42693
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the ACPI specification, version 6.3:
OSPM accesses GPE registers through byte
accesses (regardless of their length).
So, reporting dword-sized access is wrong and means nothing anyway.
Tested on Asus P8Z77-V LX2, Windows 10 still boots.
Change-Id: I965131a28f1a385d065c95f286549665c3f9693e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They only differ in rather small details, so we can iron them out.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I01907f1b8576e82c74b7beeea31ae8ee3e2cc773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42010
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 9550e97 [acpi: correct the processor devices scope] changed
the default CPU scope from _PR to _SB, but the default prefix in
Stoneyridge's Kconfig was missed, leading to ACPI errors for
'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and
eliminate the errors reported in dmesg.
Test: boot Linux w/5.3 kernel on google/liara, check for errors
Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide common initialisation point for setting up
GNVS structure before first SMI is triggered.
Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the delbin variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158797761
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_DELBIN
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The dptf.asl is needed when creating a new volteer variant, otherwise,
it will make the variant build failed. The error could be found from
this link: https://review.coreboot.org/c/coreboot/+/42709
BUG=b:158797761
TEST=Generate the Delbin correctly
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The EC firmware is 128k including its header, so there's no need to
reserve another 4k for the header.
TEST=Mandolin still boots.
Change-Id: Id3a7a087bf37461ca8ad3da9a809f13d7f0d570c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42705
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the wyvern variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158269582
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_WYVERN
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the faffy variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
V.2: Manually modified to keep Kconfig sorted.
BUG=b:157448038
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_FAFFY
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch USB2 port1 and port3 due to circuit change from rev0.
BUG=b:154071868,b:154585046,b:156429564
BRANCH=none
TEST=none
Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.
BUG=b:149714955
TEST=lid/base touch screen works correctly
Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Here we consolidate some of the mainboard.c duplication between
Puff and it's variants.
Customizations can be done later via introducing a devicetree
parameterisation.
BUG=b:154071868
BRANCH=none
TEST=none
Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the changes added in
commit 80df052d3 "cbmem: Add IDs for TSEG and BERT table data"
No platform uses either ID. TSEG in cbmem is incompatible with stage
cache. BERT reserved data in cbmem is unusable in Linux.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42532
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso's BERT region should not have been moved to cbmem in commit
901cb9c "soc/amd/picasso: Move BERT region to cbmem". This
causes an error of "APEI: Can not request [] for APEI BERT registers.
FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG. Remove the cbmem reservation and locate the region
by searching for the HOB.
BUG=b:136987699
TEST=Check that BERT is allocated
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For some reason, one printk statement begins with `HD Audio` instead of
the more common `Azalia`. Change the different prefix for consistency.
Change-Id: Ia79e340f331b9186cc09b04f925ff9d94204955e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The code is pretty much the same, only differing in a comment and a
printk statement.
Change-Id: Ic404ef466636fc05c2baa70aad8a39bb1b458d42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reflow some comments and add spaces around an operator.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I655d74ecbefa664d79b1af805f92cbcf877a43ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Both i82801gx and i82801jx start with the LPC setup function. For some
reason this isn't reproducible, but it should not effect functionality.
Change-Id: I9d26a151757d60e56ed70181ff7aef48e229d322
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
For consistency with other Intel southbridges, we rename this function
to `i82801ix_lpc_setup`.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Id8b3bcc9174277e085868866a1b5d90b5c51201a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
These southbridges are not i82801gx.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I6b4c7bc11bcb668adb0aae463defea982cf9059c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update to the latest auto-generated UPD files. Add the GUID for the
BERT HOB now being reported.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ia01f626bc85696483173b567bb4f06d308832a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42529
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP
UPD via dev tree.
BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The comment fits in 96 characters, so do it, also getting rid of the
unwanted multi-line comment style.
Add a dot/period to the end of the sentence.
Change-Id: I7b5c7ea5da00d649aa06361e0e0cf2431874a6ec
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename function from xeon_sp_get_cpu_count()
to xeon_sp_get_socket_count().
This function returns CPU socket count, by getting it from the field
named as numCpus in FSP HOB.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Furquan Shaikh