These methods had unused arguments and could be corrected by
setting the correct number in the method initializer.
Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.
Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This field is not provided by the soc code so add it.
TEST=Check the output of 'dmidecode -t memory'
Change-Id: I6fdf3520da62336a5c654575ed8d1f33eb4f4dc5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It’s unclear why this option was commented out. Activate the line, and
copy the CMOS layout and defaults from qemu-i440fx.
TEST=Boot 2.11.1(Debian 1:2.11+dfsg-1ubuntu7) and see that nvramcui
works. A changed value doesn’t survive a reboot though.
Change-Id: Ieef86f092d323c68a6d2d0cc6c04c395f743a935
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26265
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix dual LAN sku can't inherit correct MAC from VPD setting.
BUG=b:77836343
BRANCH=Fizz
TEST=Program the mac address to VPD in shell
vpd -s ethernet_mac0=<mac address1>
vpd -s ethernet_mac1=<mac address2> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/25587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the gpio configuration structure to the intelblock format.
The resulting configuration is functionally similar (even if some
bits are not identical).
Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25424
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).
- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock
Note: There is no functional change in this patch.
Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is based on the code from the 8470p port. Tested on the quad
core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics
cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The
laptop must be completely disassembled down to the motherboard to
perform the initial flash, subsequent flashes can be done internally
via flashrom. There is a simple mod that can be performed to make
subsequent external flashes easier in case of a brick, I'll put more
information on this on the wiki later. The lack of an MXM structure
built in to the firmware causes the GPU to enter a mode with nerfed
performance, there is a workaround though, I'll add this to the wiki
as well. I have no info on EHCI debugging.
Tested and working:
- memory: 4G+4G, 4G+4G+4G+4G
- Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload
with graphics init disabled in coreboot. I allowed SeaBIOS to load the
VBIOS from the MXM.
- WLAN
- keyboard, trackpoint and touchpad
- USB
- serial port on dock
- fan control
- VGA
- DisplayPort
- Audio
- Both HDD SATA ports, ODD SATA, eSATA
- S3 with SeaBIOS 1.11, SERCON must be disabled
- Brightness and volume FN keys
- Mute and calculator hotkeys
- Status LEDs
- Bluetooth
Not working:
- GRUB2 as payload will freeze. Has something to do with at_keyboard
module. The built in keyboard requires this module to function though.
- Sleep FN key
- WiFi toggle and internet browser hotkeys
- S3 fails to resume (restarts) if the laptop is removed from AC power,
or gets unplugged and then plugged back in while suspended. Sleep
status LEDs remain normal during this process.
Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a
Signed-off-by: Robert Reeves <xiinc37@gmail.com>
Reviewed-on: https://review.coreboot.org/23651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.
BUG=b:79396300
Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so
I'm renaming librem_bdl into librem_bdw and changing the KConfig
options accordingly.
Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26237
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms
BUG=b:78541692
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26214
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without it the PS/2 keyboard doesn't work after booting into the OS.
Change-Id: Idcb0ea0779fcd5dfd6e0fbf33a532ecf0caec420
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/26131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different
Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Convert the purism/librem13v1 to a variant setup, in
preparation for adding the librem15v2 board as a new variant.
The Librem 13 v1 and Librem 15 v2 are nearly identical, so
this minimizes new code to add support for the latter.
Also update the URL in board_info to an archive.org link.
Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This adds a new SPD entry for samsung's new 4GB memory and updates
atlas to use it instead of the previous gen memory.
BUG=b:79444337
TEST=booted on atlas
Change-Id: I19567736c45a1321586378c3d964c2cbebe24755
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/26185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This keeps Audio clock and data pins ON in S0ix to support
Wake on Voice.
BUG=b:77605180
BRANCH=none
TEST=Checked that S0ix suspend/resume works. Validation of WoV
was done on glkrvp previously. For Yorp, audio topology firmware
updates are required for testing WoV.
Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.
A name cannot be defined and declared external in the same table (GPID)
A name cannot be defined and declared external in the same table (CTOK)
Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26122
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.
2) I2S2 is used for Boot Beep.
So, update GPP_F0 ~ F2 pins accordingly.
3) Include DMIC-4ch configuration.
BUG=b:79362472
TEST=None [Waiting for HW to verify]
Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Video Bios Table to improve user experience when running
coreboot's blob free graphics init.
As it's not a binary blob it should not be added to the blobs repo.
This is taken from vendor BIOS and contains purely documented
configuration data, so it should not be subjected to copyright.
Extracted using intelvbttool with applied patch
I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool"
Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.
The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.
BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.
Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Incorrect interrupt routing configuration prevented handling
interrupts for devices behind PCIe bridges 00:02.1 and 00:02.5.
With the new configuration, devices work as expected.
Tested with Linux 4.10 booted with the "pci=nomsi" parameter.
Change-Id: I3c95be7ba6207697afc7983d4b5f9d9a28584723
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I6efd1675b1124b200b5ff16fdef91c10b77b69d1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I7f1276ee593928956913eaeecd62fd3018cc9ae2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I4b2b8593c98791dac7a5c016e75d2c05bcfbf890
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I15f160c1e30496461f7100e3bd3a2e2467c64c4a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I8fe817bb514c69a647c2208a0573a2c5fe98722d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I6fc056acb8ff16a943352342b99a9ede6558d438
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I01270248bddf07df4c959f0c632e722728d0cd03
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I75258ecc5f3881012c3f767c8b970a1f10c6abbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: If4ec2e2e7cca8d8f3e5abfd9cd204f86e367b44a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I5928e871b8e9ba5964c02fbabb7a9d8dc9ecc0a8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch adds subsystem_id for eve as 0x006B. The value
is set in nhlt structure which will be used by endpoints as well.
Change-Id: Id6910678c4d6e92ed45c776f174855efd26f9e27
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change:
1. Allows mainboard to add OEM table to CBFS
2. Provides mainboard specific smbios_mainboard_manufacturer that reads
OEM ID from EC using CBI and compares it against the OEM ID in CBFS
table to identify the right OEM string.
BUG=b:74617340
Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I3857d7ef4eb02974aabe3029abb49efb218cbd93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ib9c0d0a85a9e38cdb1bdbcfa055e597f19cf3d5c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ie5ed621423315388e2b8eb3d5433ef2a7a47d602
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ifc9d82270513f4b4f34d9cf210c37029202b5a5f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I93b2ce6a26b3a64bd6f4e4c827e9f551b37c6dd0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Use of device_t has been abandoned in ramstage.
Change-Id: Icf7c99ca55d2bcbca2c974d59a63e89758ba5ea6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: If67ea25a9e1363dde8aefe62b92ee7a61f0458b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I8c6358d072b25ab4758637da989883daa600c8ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ie6a8364bdd272515e1567061ae0b117392c268aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Icc633dc499568cf672f5e244e026e45a6eea5fd8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
