Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC
from internal nami/vayne thermal team. Add conditional compilation
in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl.
BUG=b:72974136
TEST=Match the result.
Change-Id: I4b593118ca460a59aa49786cb99df417d135112a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add APIs and required parameters for creating Realtek 5682 SSP
endpoint in NHLT table.
BUG=b:79235534
TEST=check that NHLT table defined is created properly.
With the series merged & required driver support in kernel.
Verify Headset Audio playback.
Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/26057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix tables and minor markdown bugs.
Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These methods had unused arguments and could be corrected by
setting the correct number in the method initializer.
Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.
Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This adds the following changes to the blobs repository:
78a02a7 cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
In short: Bump Intel microcode updates. They include spectre/meltdown
mitigations.
Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/26270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Make use of i8042 driver to add PS2 mouse driver support.
Tested on Lenovot T500.
The touchpad can be used to drive the mouse cursor.
Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Program the Super I/O to turn the machine on or restore its power state
when AC power is restored.
Based on code from src/superio/nuvoton/nct5572d/superio.c.
Change-Id: I1f3432f43b0784c3696bf1d7233b83d3a203af20
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/25463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This field is not provided by the soc code so add it.
TEST=Check the output of 'dmidecode -t memory'
Change-Id: I6fdf3520da62336a5c654575ed8d1f33eb4f4dc5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Make use of i8042 driver in keyboard.c.
Required to add PS/2 mouse support.
Tested on Lenovo T500.
Change-Id: If60b5ed922b8fc4b552d0bfd9fe20c0fd6c776bf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18596
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, adding a payload to CBFS using the build system, the warning
below is shown.
W: Unknown type 'payload' ignored
Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.
Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.
Required to support PC keyboard and PC mouse at the same time.
Tested on Lenovo T500.
Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It’s unclear why this option was commented out. Activate the line, and
copy the CMOS layout and defaults from qemu-i440fx.
TEST=Boot 2.11.1(Debian 1:2.11+dfsg-1ubuntu7) and see that nvramcui
works. A changed value doesn’t survive a reboot though.
Change-Id: Ieef86f092d323c68a6d2d0cc6c04c395f743a935
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26265
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix dual LAN sku can't inherit correct MAC from VPD setting.
BUG=b:77836343
BRANCH=Fizz
TEST=Program the mac address to VPD in shell
vpd -s ethernet_mac0=<mac address1>
vpd -s ethernet_mac1=<mac address2> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/25587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is a special case for the Fizz firmware branch, when the device index
is 1, it will check "ethernet_mac" first and then "ethernet_mac0".
For single NIC: config.device_index = "1", maps to "ethernet_mac"
For multiple NICs: config.device_index = "1", maps to "ethernet_mac0"
BUG=b:77836343
BRANCH=Fizz
TEST=Add device index in device tree &&
Program the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/26051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.
Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.
Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Braces {} are not necessary for single statement blocks.
Change-Id: I2a2d8672fe3f53450dcfa53dc127b89b4aa6b75e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In some cases callers want to know if a file
exists and, if so, what its type is.
Modify cbfs_locate so that if the pointer is non-NULL,
but has the value 0, the type of the file that
matches the name will be returned.
Change-Id: Ic1349d358c3054207ccbccf3825db56784327ad0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update the gpio configuration structure to the intelblock format.
The resulting configuration is functionally similar (even if some
bits are not identical).
Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25424
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).
- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock
Note: There is no functional change in this patch.
Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All those symbols are part of /include/symbols.h file hence
removing from /security/vboot/symbols.h
Change-Id: Id968186e28d6b772a1a6bca200a852407324d6e3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The NPCD378 can be found on at least:
* HP Compaq 8200
* HP Compaq 8300
The datasheet is not publicly available, as HP implements lots of
custom hardware. Add basic support for it, based on HP Compaq 8200.
The first eight LDNs seem to be standard nuvoton compatible, except for
LDN4, which is used to control front LED and power in ACPI S3.
LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's
IOBASE with a size of 0x100 bytes.
The HWM consists of 16 pages with each holding 0xff bytes. The pages can be
selected by writing the page index to IOBASE + 0xff.
TODO:
Reverse engineer the HWM to support fan control.
WARNING:
The remaining LDNs have been guessed and might be wrong!
The serial has been tested and is working.
Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25384
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to extend the MP callback infrastructure prepare for
easier changes by making the AP callback get signalled by a
single pointer to a local variable on the signaller's stack.
When the APs see the callback they will copy the structure
to a local variable and then set the acknowledgement by
clearing out the slot.
The reading and writing to the slots were implemented using inline
assembly which forces a memory access and a compiler barrier.
BUG=b:74436746
Change-Id: Ia46133a49c03ce3ce0e73ae3d30547316c7ec43c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapt the programming of initial DLL values for DDR3.
Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Also throws in some minor fixes like the wrong conditional for
bankmod and using real CAS when programming MCHBAR(0x248).
Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adds nmode to the sysinfo struct as it is needed later on.
Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19872
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A few values were wrong, but it does not seem to matter all that
much.
Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19871
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.
Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since this memory controller supports both DDR2 and DDR3 allow it to
decode both while making the dram type mutually exclusive.
Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some things in programming registers related to dual channel
interleaved operation were wrong.
This also adds some code that could in the future be used when me is
active and claims some memory for its UMA.
This also uses some more sensible variable names to clarify at least
some of the magic.
This fixes memtest86+ failing with some assymetric DIMM configuration.
TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM
configuration setups (would instantly fail at addresses above 4G on
many configurations).
Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add an lpc_acpi_name function to report its namespace as "LIBR"
rather than some fallback value which seems to vary. This repair
is required for the LPC TPM device to register its presence
without blowing up the table and preventing the payload from
seeing the SATA device.
Before change (but after other similar change to PCI0), the
TPM device reported itself as:
\_SB.PCI0.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LIBR.TPM
which is consistent with the tables AGESA generates.
Change-Id: Ifa3a0e386cc00062855331e5f9d1c00d6541c238
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a function domain_acpi_name to return "PCI0", rather than
falling back to the parent' device's "\_SB" label. This repair is
required for the LPC TPM device to register its presence without
blowing up the table and preventing the payload from finding SATA.
Before change, the TPM device reported as:
\_SB.\_SB.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LPC0.TPM
A separate change submission will correct "LPC0" as well.
Change-Id: I5e8d4715c9b42f50c84dd65818e4b0fdfc9d54f9
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I'm increasing the max because when AGESA tracing is enabled it will use
over 120 entries. I added some padding to the number incase more probes
are added. This only affects ramstage so the extra ram shouldn't matter.
BUG=b:64549506
TEST=boot on grunt and ran cbmem -t
Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This will allow loading of programs that are more than one type,
e.g. ramstage type might now be a stage or payload.
Further, unknown types of 0 are dangerous, make it a real value.
Change-Id: Ieb4eeb7c5934bddd9046ece8326342db0d76363c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Had 0x2e hardcoded, which is often the SuperIO chip. Instead,
pull the port from the PNP tree generated from devicetree.cb,
where either 0x4e or 0x2e will be specified.
Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
John Su