These parts have not been used in any vilboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=vilboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611994
TEST=none
Change-Id: I99614acaf45db0556120c883577494d9f753ea12
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45679
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.
BUG=b:165611994
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Morphius has SSD/eMMC SKU, we should turn off eMMC
if storage is NVMe SSD.
BUG=b:169211959
BRANCH=zork
TEST=1. emerge-zork coreboot
2. Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Change-Id: I67d5d77ce3d827ae89b82529de59925f67eaf894
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
While we're at it, fix up cosmetics on a few comments. The GADD method
seems to suffer from copy-paste symptoms. A follow-up will address this.
Some methods deliberately remain untouched in this commit, so as not to
collide with another patch train that already takes care of them.
Tested with BUILD_TIMELESS=1, Intel Ice Lake U RVP does not change.
Change-Id: I613f5f65638b92ca23f3ce15a15dd063afa52c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
While we're at it, fix up cosmetics on a few comments.
Some methods deliberately remain untouched in this commit, so as not to
collide with another patch train that already takes care of them.
Tested with BUILD_TIMELESS=1, Purism Librem 15v4 does not change.
Change-Id: Ib27c5b48459e3ea7eabc34457cb204994ee9b617
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45691
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves gpio_op.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify all methods present inside
common gpio_op.asl like GRXS, GTXS etc. are still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TEST=Able to build and boot EVE platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there
2) Verify no ACPI error seen while running 'dmesg' from console
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: I02df3ddf5ad33d42d97feefb0fa366ad8c856565
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45681
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Able to build and boot ICLRVP platform.
1) Dump and disassemble DSDT to ensure GRXS function implementation
remain unchanged prior and after this CL.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros.
TEST=Able to build and boot CNL and CML platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first
and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number.
Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BOOTBOOT is a multi-platform, architecture agnostic boot protocol.
The protocol describes how to boot an ELF64 or PE32+ executable inside
an initial ram disk image into clean 64 bit mode. This version uses
libpayload to do that. Depending on the lib's configuration, initrd
can be in ROM as a cbfs file or a Flashmap partition; on disk a GPT
partition or a file on a FAT formatted ESP partition.
For more information see https://gitlab.com/bztsrc/bootboot
Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0
Signed-off-by: Zoltan Baldaszti <bztemail@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With MAX_CPUS==1, this has the effect of removing spinlock
implementation. But since is_smp_boot() evaluates false and
SMM uses separate smi_semaphore, there is no concurrency to
protect against with a spinlock.
Change-Id: I7c2ac221af78055879e7359bd03907f2416a9919
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Looks like the option is generally not compatible with
garbage collections. Nothing is inlined, is_smp_boot()
no longer evaluates to constant false and thus the symbols
from secondary.S would need to be present for the build
to pass after we set SMP=n.
Change-Id: I1b76dc34b5f39d8988368f71a0a2f43d1bc4177e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43817
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The config string is HAVE_SPD_IN_CBFS, without the "BIN".
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I728f64b2dd93b0e3947983b9b3701e185feff571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.
Alder Lake is not yet complete, so it has been skipped for now.
Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Though only one platform uses it, this will save some redundancy.
Change-Id: Ic151efe5dd9b7c89f779ac3e10c3a045f07221d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This adds eMMC preset settings.
It also fixes some formatting and a comment.
BUG=b:159823235
TEST=Build test
Cq-Depend: chrome-internal:3251807
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.
BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork
Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Align groups of definitions, reflow long lines and adjust whitespace.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I75723fe087ef16f74ca93f6faa4d3468d7958a5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It primarily contains definitions for MMIO windows. Also, remove
includes from files not directly using the definitions it contains.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: Id28080d9b2924463dd3720492d5e717d65fa0071
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to have implementation details in a public header.
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: I0bfd6ee72347249302ee073081f670b315aa40e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Align groups of definitions, reflow long lines and adjust whitespace.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: I2969274c6b50f56994e45ada5d016504addfc13e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
There's no need to wrap these macros with casts. Removing them allows
dropping `uintptr_t` casts in other files. Changes the binary, though.
Change-Id: I1553cbeee45972d6deba8cb9969c69fceeb19574
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45432
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the boldar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
Add "memory/Makefile.inc" generated by gen_part_id.go
BUG=b:162202257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_BOLDAR
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.
Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0
syntax across CNL, ICL, JSL, SKL.
TEST=Able to build and boot Hatch, EVE and ICLRVP platform.
Dump and disassemble DSDT to ensure GRXS,GTXS etc functions
implementation remain unchanged prior and after this CL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In addition to CB:45664, rename clevo/l140cu to clevo/cml-u being able
to add more variants under a generic mainboard later.
Change-Id: I9c16e24830ebb80752df302aa2e63d9df8edad95
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45665
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clevo mainboards can be grouped by their common platform. Therefore,
restructure the mainboard directory as a first step, so that the variant
mechanism is used.
This moves most of the code into the variant dir, since the L140CU is
the only variant at the moment.
Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.
The only difference between the two is the usage on macros in common
code instead of plain integer values.
Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.
BUG=b:169045123
TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP
configuration. Booted up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naveen M <naveen.m@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Amanda Huang