Commit Graph

8924 Commits

Author SHA1 Message Date
Vladimir Serbinenko 7905f9254e qemu: cirrus native video init
Recent commit proposal by Ron Minnich proposes to move to native gfx init for
qemu. Unfortunately we didn't have native init for default qemu video (cirrus)
Here is one extracted from GRUB one which I wrote couple of years ago.

Change-Id: Icb89cf918ef5d276bcc703c48c568e7b9c1be756
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4270
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 20:40:58 +01:00
Vladimir Serbinenko c6f6be0929 Support for nehalem northbridge
Including raminit

Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25 20:23:38 +01:00
Vladimir Serbinenko 888d559b03 Support for Ibexpeak southbridge
Part of X201 port.

Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4052
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-25 19:32:36 +01:00
Ronald G. Minnich cae09e0bbe bochs: add support for native graphics
Per our discussions with Gerd, qemu will now always do native graphics
on coreboot. The VGA BIOS capability is not needed and will no longer
be supported. Attempts to build without native graphics will result in
an error.

This code builds for both x86 emulation targets. I'm hitting an issue
testing that is unrelated to coreboot; if someone can test, that
would be helpful. Be sure to start qemu with -vga std.

We also add a test for the PCI BAR being zero and return silently if it
is.

Change-Id: I66188f61e1bac7ad93c989cc10f3e0b55140e148
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4258
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2013-11-25 18:31:25 +01:00
Vladimir Serbinenko 969553e574 Add declaration of dock registers 1, 2 and 3.
Needed to make dock work on X201.

Change-Id: Id0b32266cacf04bb48530bedf50818c268f947ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4081
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-25 07:00:11 +01:00
Alexandru Gagniuc 655ac2420d google/butterfly: Declare mrc_scrambler_seed_chk in cmos.layout
SandyBridge raminit uses this CMOS option. If it is not declared, the build
fails when USE_OPTION_TABLE is selected.

Change-Id: I1ba1f994d4ea3824dc66e8f35d0b5b24b88d4dd6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4269
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 04:11:46 +01:00
mrnuke a0ca7d0458 .gitignore: Properly ignore KDevelop files
Change-Id: I1410242e4d1995baedd5d3a001f86619e729db98
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4268
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-25 02:12:58 +01:00
Vladimir Serbinenko 5183ab64b5 no-car/cbmemc: Fix compilation
the part !CAR && PRE_RAM is obviously meant as dummies. Unfortunately
cbmemc_tx_byte has wrong number of arguments and hence causes compilation
failure.

Found out when compiling for vexpress-a9.

Change-Id: Ic84d142bac5c455c2371fbc9439c898de04a974e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4267
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-24 18:25:18 +01:00
Duncan Laurie 990555b0ef haswell: Update GT PM register value
This was changed to 0x80000000 in SA BWG 1.5.0.

Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4166
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:11:30 +01:00
Duncan Laurie fd0bc14844 haswell: Update ULT microcode to 0x10
[    1.503741] microcode: CPU0 sig=0x40651, pf=0x40, revision=0x10
[    1.510483] microcode: CPU1 sig=0x40651, pf=0x40, revision=0x10
[    1.517213] microcode: CPU2 sig=0x40651, pf=0x40, revision=0x10
[    1.523947] microcode: CPU3 sig=0x40651, pf=0x40, revision=0x10

Change-Id: I19ef40b636eebeb8cc29cc0404abbe263ec8eaa7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50655
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4165
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:11:04 +01:00
Duncan Laurie 1c09710709 haswell: Remove limit on package C-state
With the XHCI controller enabled we no longer hang the
system when dropping into a package C-state so remove
the code that was disabling it.

Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50355
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4163
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:10:46 +01:00
Duncan Laurie 58181124f6 haswell: Update ChromeOS ACPI GPIO package
The chromeos_acpi driver sysfs naming is not what
crossystem expects if there is just one entry in the package
because it does not add a ".#" suffix in that case.

Specify all the expected GPIOs on wtm2 as undefined, which
should be 0xFF and not 0x00 becuase 0 is a valid GPIO.

Change-Id: I9b17e9bab94219695e65b17914c84acf02a0983b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4162
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:10:08 +01:00
Aaron Durbin 5b4178575f haswell: split microcode between ULT and non-ULT
The current microcode blobs contain both ULT and non-ULT
revisions. Only include one or the other based off of the
CONFIG_INTEL_LYNXPOINT_LP Kconfig option.

Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50318
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4160
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:08:39 +01:00
Aaron Durbin 8e0cd496a1 haswell: enable monotonic timer
For all the current haswell boards enable the monotonic timer.
The ULT boards use the 24MHz MSR while the non-ULT boards use the
local apic.

Change-Id: I8b19f526a5a49e8467f296c566a2c4263bc5a863
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49763
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4148
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:07:53 +01:00
Duncan Laurie 3e996a55cd haswell: Update ULT microcode to rev 'a'
Change-Id: I714208da23bf7cbd1232874c05ad3100551f5f7c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49647
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4146
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:04:36 +01:00
Duncan Laurie e1e87e0ed6 haswell: Configure PCH power sharing for ULT
This reads PCH power levels via PCODE mailbox and writes the
values into the PMSYNC registers as indicated in the BWG.

Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4143
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:04:12 +01:00
Aaron Durbin f24262d018 haswell: calibrate 24MHz clock against BCLK
On haswell ULT systems there is a 24MHz clock that continuously runs
when deep package c-states are entered. The 100MHz BCLK is shut down
in the lower c-states. When the package wakes back up a conversion
formula needs to be applied. The 24MHz calibration is done using the
internal PCODE unit.

Change-Id: I6be7702fb1de1429273724536f5af9125b98da64
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48292
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4136
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:03:18 +01:00
Aaron Durbin 7c35131642 haswell: configure c-states
The c-states are configured according to the BWG, however the
package c-states are disabled as they currently cause platform
instability. The exposed ACPI c-state to processor c-state mapping
are as follows for ULT boards:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C7S long latency)
	ACPI(C3) = MWAIT(C10)
The non-ULT boards have an expoed c-state mapping:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C3)
	ACPI(C3) = MWAIT(C7S)

Included in this patch is removing the updating of current limit
registers as some of the MSRs are different and the proper values
are currently unknown. Lastly, some of the MSRs were renamed to
match the BWG.

Booted 3.8 kernel and used powertop to note package, core, and acpi
c-state residency.

Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48291
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4133
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:01:38 +01:00
Duncan Laurie 15de7cb422 lynxpoint: Add a function to set an individual GPIO
This will be used in a later commit to do some specific
power sequencing.

Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4137
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 08:45:25 +01:00
Duncan Laurie 55ad972432 lynxpoint: Rework LP GPIO handling
This adds some macros for the common GPIO defines and drops
the gpio number definition from each entry.  The end result
is much easier to read.  The wtm2 mainboard gpio list is modified
to use this.

Also fix a bug in the LP version of get_gpio() that was always
returning zero due to a miscompare.

Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48946
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4138
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 08:02:51 +01:00
Duncan Laurie 0edc22490a smi: Update mainboard_smi_gpi() to have 32bit argument
With the LynxPoint chipset there are more than 16
possible GPIOs that can trigger an SMI so we need
a mainboard handler that can support this.

There are only a handful of users of this function
so just change them all to use the new prototype.

Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49530
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4145
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 07:40:22 +01:00
Duncan Laurie a7e9a9b75f slippy: Add panel power sequence timings
These are placeholder values until we can configure for
the exact panel.

Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4196
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:28:50 +01:00
Duncan Laurie d80cd2ad80 slippy: Clean up for easier porting
Minor tweaks to variable names in the slippy mainboard
that make it easier to base a new board from without
as much renaming.

Also properly set up the thermal variables for the
thermal zone that is defined in ACPI instead of using
the generic setup from WTM2.

Change-Id: I752c1a50bfdc06b6ddad95bd1331c6870b9f9df2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56328
Reviewed-on: http://review.coreboot.org/4183
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:26:30 +01:00
Duncan Laurie cfe0235c6f slippy: Run EC init as part of mainboard init step
This will log and clear EC events so they do not take effect
when the SMI handler is enabled.

Change-Id: I5ef563f7cedc8977410cc3f69e2655fc4e14c9eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4178
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:24:20 +01:00
Duncan Laurie 90bfbfa9ba slippy: Update interrupt routing
The SerialIO devices have specific requirements for PCI
interrupt mode to use PIRQ{E,F,G,H} that are not being met.

D21:F0 uses PIRQE, which must not be shared with other PCH
D21:F1-F6 share PIRQF, which must not be shared with other PCH
D23:F0 uses PIRQH, which must not be shared with other PCH

- Fix D20IR -> D20IP typo
- Remove D25/EHCI2 as it does not exist
- Reorder other interrupts to clear PIRQE/PIRQF/PIRQH

Check device interrupts in the kernel

0:      IO-APIC-edge    timer
1:      IO-APIC-edge    i8042
8:      IO-APIC-edge    rtc0
9:      IO-APIC-fasteoi acpi
16:     IO-APIC-fasteoi ath9k
18:     IO-APIC-fasteoi i801_smbus
19:     IO-APIC-fasteoi ehci_hcd:usb1
21:     IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1
40:     PCI-MSI-edge    PCIe PME
41:     PCI-MSI-edge    i915
42:     PCI-MSI-edge    ahci
43:     PCI-MSI-edge    xhci_hcd
44:     PCI-MSI-edge    snd_hda_intel

Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:22:51 +01:00
Aaron Durbin a54adc1bc7 slippy: set PWM values
The dev screen was not displaying properly. With the
PWM values programmed the screen displays correctly.

Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51472
Reviewed-on: http://review.coreboot.org/4172
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:22:16 +01:00
Duncan Laurie 270881af74 slippy: Put SerialIO devices in PCI mode
The device at function 0 also needs to be enabled
or the kernel will ignore all other functions.

00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03)
00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03)
00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03)

Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51370
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4171
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:21:49 +01:00
Duncan Laurie ffa0fa4660 slippy: Add EC to the device tree
This lets the keyboard init get called properly.

Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4167
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:20:37 +01:00
Duncan Laurie 4d019c9ee2 slippy: Update SPD
Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50082
Reviewed-on: http://review.coreboot.org/4157
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:19:46 +01:00
Duncan Laurie f31fcbc832 slippy: Add SPD data for on-board memory
Change-Id: I7a617fe06d23b906f718ed30f1378f7d220b2799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4154
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:18:21 +01:00
Duncan Laurie a103d0715c slippy: Prepare LPC IO decode ranges for EC
- 0x200-0x208 for host command window
- 0x800-0x8ff for host command arguments and parameters
- 0x900-0x9ff for exported EC memory map

Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49755
Reviewed-on: http://review.coreboot.org/4151
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:17:31 +01:00
Duncan Laurie e820a6ce83 slippy: Add iSSD power sequencing
Without an LM10506-A the power sequencing for this
part needs to be done manually using GPIOs.

Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49648
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 06:16:48 +01:00
Duncan Laurie cf72d91613 slippy: Initial mainboard commit
Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49531
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4147
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 06:15:12 +01:00
Zheng Bao 7797ffa1be amd/olivehill: Fix the double spaces in copyright header
Change-Id: I1bdc52efc827c331c53b97d2b96edafc518d05bf
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4259
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-24 06:07:15 +01:00
Bill Richardson 6a89cf3ef3 Honor vboot's request to load the VGA option ROM
This removes an earlier patch that caused the VGA option ROM to be loaded by
coreboot even in normal mode when it isn't needed.

Change-Id: Ie0a331a10fff212a2394e7234a0dbb37570607b7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48173
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4125
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:42:16 +01:00
Stefan Reinauer 047c98a2c1 libpayload: fix wrong endian assumption in sha1.c
Not all platforms !x86 are big endian, hence actually look
at the CONFIG_LITTLE_ENDIAN flag instead of CONFIG_ARCH_X86.

Change-Id: Ibbd8f48b377a1121dd1e045834a94a2d67eda2ab
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/56066
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4236
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:40:19 +01:00
Peter Stuge c6f0997ffc Northbridge: i945: Native VGA init: print the GMA and GTT addresses
The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:38:51 +01:00
Peter Stuge 03e4ac6671 Northbridge: i945: Native VGA init: use UMA address
The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: I4e88c26b70ea8cb249d7613c749b3edc5e3b5e7f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4000
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:38:02 +01:00
Peter Stuge c882d93054 Lenovo X60: Native VGA init: Get rid of the memory corruptions.
Without that fix the GTT points at 0x00000000.

The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: Ia378b600ba2faf00d42635c6503b94ff0cb1bc8c
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:37:36 +01:00
Denis 'GNUtoo' Carikli 2186b6538e lenovo/x60: native vga init: fix code style issues.
Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3999
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:37:02 +01:00
Andrew Wu 33b09567d2 dmp/vortex86ex: Move DMP specific POST code defines into one file
Move into src/cpu/dmp/dmp_post_code.h

Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3989
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:36:36 +01:00
Denis 'GNUtoo' Carikli 099b914dcd lenovo/x60: export reboot_bits nvram configuration.
This permits any software running after the ramstage to tell coreboot that the
  boot was successfull.

Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3992
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:35:38 +01:00
Paul Menzel f3c1c9b6ac payloads/external/SeaBIOS/Makefile.inc: Remove empty lines at file beginning
Change-Id: I3e6eba62b6790836edf9813c2a45c77390d8c078
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4094
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:34:47 +01:00
Duncan Laurie 25b8b7b881 haswell: Put each logical processor in its own P-state domain
The recommendation from Intel is to report each core as a
separate logical domain in the _PSD table.

This goes against the recommendation in the ACPI specification
because all of these cores are on the same package and share a
VR so they will do voltage transitions together.

The reasoning is that with a larger number of logical processors
the P-state often ramps too quickly resulting in higher power
consumption.  By exposing each core as a separate domain the OS
can manage them individually allowing the socket to select the
optimum frequency.

$ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT
$ iasl -d /tmp/SSDT

Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000000,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000001,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000002,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000003,
      0x000000FE,
      0x00000001
    }
  })
}

Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4130
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:34:25 +01:00
Duncan Laurie 77647b33cf haswell: Update microcode for ULT/40651 to rev 8
$ cat /sys/devices/system/cpu/cpu*/microcode/version
0x8
0x8
0x8
0x8

Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4129
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:31:06 +01:00
Duncan Laurie 7a91816bdb Fix compile error in chromeos by adding stddef.h
Compile was failing with the following error:

In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0,
                 from src/vendorcode/google/chromeos/chromeos.c:22:
vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t'
src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload':
src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function)

Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48289
Reviewed-on: http://review.coreboot.org/4131
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:30:10 +01:00
Vladimir Serbinenko d26558cf5b Lenovo hotkeys support
Implement proprietary lenovo ACPI hotkeys

Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4055
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 00:20:04 +01:00
Vladimir Serbinenko 219f068ae3 Change EC GPE on X201
X201 has GPE at 0x11 (17) instead of 28.

Tested on X201.

Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4053
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23 23:41:12 +01:00
Vladimir Serbinenko 617f853ae4 lib/coreboot_table: set type and size of framebuffer tag after fill_lb_framebuffer
When testing Ron's patch on qemu I found out that fill_lb_framebuffer
overwrites size and tag fields. We need either to fix/check all
fill_lb_framebuffer implementations or write tag/size after fill_lb_framebuffer.
I prefer later as it's more robust.

Change-Id: I98f5bac14f65fb4d990cb21426d402b27f2e8a48
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4263
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23 18:40:40 +01:00
Vladimir Serbinenko 71f35ebdaa Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
2065x is with nehalem and not sandybridge.

I don't care much eitherway but it clears some confusion.

Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4046
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-23 14:32:29 +01:00