The current lpddr4 skus entries do not match the RAMID table in the
schematic. This commit updates that so they are consistent. Thankfully,
the values are the same as for glkrvp, so I just copied from there.
BUG=b:74392818
TEST=None
Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following gpios are no longer needed and are now configured as
no-connects : GPP_C6, GPP_H4, GPP_H5
BUG=b:74406599
BRANCH=master
TEST=none
Change-Id: I55769336195db0e57dfbaf5b5770e15050138341
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that fields that are not updated in
variant_memory_params keep a default value of 0.
In particular, use_sec_spd is intended to have a default value of
0 on all platforms. Without this patch, a random value is used
and all boards (except nami) get stuck on boot.
BRANCH=poppy
BUG=b:74439917
TEST=Nautilus and poppy can boot, and do not get stuck at
"CBFS: 'sec-spd.bin' not found."
Change-Id: I06c6511625de930903ae13788bdcd27667a17886
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/25101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
we had disabled software sync for bringup - we now have enough
functionality in place to turn on software sync.
Change-Id: Ib7f5a24ed8a47cb44b3f505e3cd49e0cb6931dc0
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit
[15:0] to the same value program in LPC PCI offset 82h. Also this
cycle decoding is only allowed to set when SRLOCK is not set.
Hence move the required programming from lpc.c to pch.c.
Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO
Kconfig is selected.
Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
By default all Intel platform has enable IO decode range for COMA if
CONFIG_DRIVERS_UART_8250IO is selected.
With this patch, COMB will get enable based on
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection.
Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid
an additional pci configuration read to get the same data.
Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change SECONDARY_SPD_SOURCES to SEC_SPD_SOURCES as that is what the
spd target expects.
TEST=Verified that sec-spd.bin is present in coreboot.rom
Change-Id: I4299df1eb9009095ef899c5b83823750dfc715d8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Prints the timestamp name and value to the debug console if enabled
in Kconfig.
Change-Id: Ie6e6a4877fefec45fb987ceae7d42de6ce768159
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In preparation for moving AGESA calls out of bootblock:
Add function to enable the four stoneyridge I2C engines.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation for moving AGESA calls out of bootblock:
* Add definitions for needed registers in southbridge.h
* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to
0xfed81ffff. Will be called by a later commit.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build boot Grunt (with other changes
to call code not committed at this time)
Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25025
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP can only output its traces when the HSUART PCI device is
available.
- Move the hiding to after last FSP call.
- Adapt coreboot PCI enumeration to keep the legacy configuration.
With UART configured as legacy Linux will not re-enumerate it but detects
it as legacy (ttyS0 instead of ttyS4).
Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
GPIO 40 isn't currently being used, so set it to be an input.
BUG=b:73387647
TEST=Build & boot grunt
Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Bayhub part is not used on proto with board_id 0, so disable it.
BUG=b:74248569
TEST=Build & boot Grunt. Bayhub part is disabled.
Change-Id: I635356d41bab637726594d403d66dde730f12256
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Update build so that we can get the board ID in bootblock.
BUG=b:74248569
TEST=build and boot grunt with follow-on patch.
Bayhub part is disabled.
Change-Id: I6353bcb4abcef4e8dc2b625082e33b73525c8525
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the timeout in bsp_do_flight_plan is bumped up to 1 second, this
change adds a print to indicate the amount of time it takes for all the
APs to check-in.
TEST=Verified on Nami that it prints:
"bsp_do_flight_plan done after 395 msecs."
Change-Id: I4c8380e94305ed58453ed18b341b3b923949d7a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.
The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS. In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.
BUG=b:74200887
TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and
"earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
command line, and with an image with serial console enabled.
=> System boots with (kernel) serial console enabled, starting from
0.00 (earlycon), with no gaps in its output, and serial console
also allows logging in.
Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after
initialization of cs polarity since it requires polarity to be
set to work properly. Failure to do so confuses cr50.
BUG=b:70628116
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' and verify on scope that chip select
polarity is correct for the first transaction.
Change-Id: I20b4f584663477d751a07889bccc865efbf9c469
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
coreboot's PCI resource allocator doesn't assign BAR1 for
Braswell's LPE device because it doesn't exist, but is
required by Windows drivers for the device to function.
Manually add the required resource via the existing
lpe_read_resources function, and marked it as IORESOURCE_STORED
so pci_dev_set_resources ignores it.
TEST: boot Windows 10 on google/edgar, observe that memory resources
are properly assigned to LPE driver for BAR1 and no error reported.
Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add timestamps before and after the vBIOS load and after the vBIOS
run. This lets us see exactly how long it took to load it from the
ROM chip, and how long it takes to run.
BUG=b:64549506
TEST=Build & boot Grunt, see vBIOS load & initialization times.
Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25018
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hardware updates have suggested we need to configure the K&D panel's
power sequence in software, not in hardware. Without this change, K&D
panels will no longer power on correctly and will instead display a
black screen.
Per K&D's suggestion, we tweak these two commands. From the little HW
docs I have, this looks like it's:
(Address 0xB7, Value 0x02) -> set BC_CTRL=bit(1) (Back light control) to
1
(Address 0xF1, Value 0x22) -> change GPO2_SEL=bits(0:3) from
MIPI_TE(0001b) to BC_CTRL (0010b)
BRANCH=scarlet
BUG=b:73133861
TEST=KD display with and without HW fix on Scarlet
Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/25023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like there's a typo in the GPIO state table we print as part of
assembling the coreboot tables. Of course, high GPIOs are represented as
1 and low GPIOs as 0. Fix this display bug.
Change-Id: I59b4d49955c13f920576dd09f463e2d399ab64e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Allows eMMC in PCI mode to be seen/used by Windows.
Test: boot Windows installer on google/edgar, observe internal
eMMC storage available for installation when eMMC in PCI (vs ACPI) mode.
Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch configures the gpios for all the gpio communites.
Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Per vendor datasheet, corrected linkfreq of imx258 as
{633600000, 320000000}
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/24990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We want to report the board SKU via the SMBIOS tables. Add support for
this, obtaining the ID itself from the EC.
BUG=b:74175244
BRANCH=none
TEST=manually on grunt with another CL:
mosys platform sku
0
Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.
BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).
Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The LPEA device memory resources, required by Windows drivers,
were not being set. Allocate required resources per Inte'sl CHT
Tianocore reference code.
Test: boot Windows on google/edgar, observe LPEA device working properly.
Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Certain platforms need paging enabled during cache-as-ram because
dirty lines are being evicted by a heavy speculative frontend. Paging
needs to be enabled in order to utilize the NX (no execute) bit for
the regions that are strictly data (such as the stack). This utility
creates 32-bit PAE page tables using a static address space, and
the resulting tables have entries for all the PDPTEs such that it makes
it easy to enable 2MiB naturally aligned DRAM mappings once memory is
trained. Either binary files can be generated or C files. The pages that
are linked use a default base address of 0xaa000000 that can be changed at
runtime to reflect where the page tables are actually loaded. Or
specify a physical address on the command line that is known a priori.
iomap.txt:
0xd0000000, 0x100000000, UC, NX # All of MMIO
0xff000000, 0x100000000, WP, # memory-mapped SPI
0xffff8000, 0x100000000, WP, # XIP bootblock
0xfef00000, 0xfefc0000, WB, NX # CAR
0xfef40000, 0xfefc0000, WB, # verstage
0xfef20000, 0xfefc0000, WB, # romstage
0xfef40000, 0xfefc0000, WB, # fsp-m
$ go run util/x86/x86_page_tables.go --iomap_file=iomap.txt
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 UC NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xaa000000.
BUG=b:72728953
Change-Id: I47625a24979b196011e2293712a8cdbdbb880d79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/24919
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done by overriding the weak functions from smbios.c
Some values are hardcoded as they are characteristics of the
Tagada system. Other are retrieved from the BMC through the
bmcinfo interface.
Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23843
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add more information on baseboard as described in SMBIOS Reference
Specification 3.1.1.
Change-Id: I9fe1c4fe70c66f8a7fcc75b93672421ae808bf1b
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This interface gives access to configuration information stored in flash
by the Tagada BMC before booting the SoC.
Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO.
BUG=b:73514687
BRANCH=None
TEST=None
Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add spd files for LPDDR3 based on info received from factory team.
BUG=b:73287172
BRANCH=None
TEST=None
Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Limit dependency on vendorcode header files and use defines from
iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.
BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt
Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Increase memory allocated for the LPEA firmware from 1MiB to 2MiB
to match Intel CHT reference code and fix Windows functionality.
Test: boot Windows on google/edgar, observe no error in Device Manager
for LPEA audio device due to BAR2 resource allocation.
Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Justin TerAvest