Commit Graph

2831 Commits

Author SHA1 Message Date
Carl-Daniel Hailfinger 7cb70d9abd Check for failed SPI command execution in flashrom. Although SPI itself
does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:41:02 +00:00
Carl-Daniel Hailfinger 9648351d75 Implement read support for the following Atmel chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004

I double-checked the data sheets and am confident this will work.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:36:26 +00:00
Mart Raudsepp b74fbc6122 flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITE
Tested fully on a ThinCan DBE61A

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-17 15:31:56 +00:00
Carl-Daniel Hailfinger ef3f7e38ea The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.

Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D

Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642

Add the ID, but no probing function for this chip:
AT25F512A

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-15 13:55:43 +00:00
Uwe Hermann 385e90ad1c Rename LinuxBIOS strings and filenames to coreboot.
Also, use the more generic and buildrom-friendly '../payload.elf' as
the default payload location.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14 19:25:37 +00:00
Stefan Reinauer e35d5e3fa2 drop dead code in sb600 hda
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14 13:43:26 +00:00
Marc Jones a04b107c6a Add another AM2 cpuid to the name string. Also, colapse the cases for duplicate strings to save some space.
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Chris Lingard <chris@stockwith.co.uk>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12 20:38:51 +00:00
Uwe Hermann ebb73f2dcf Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E,
IT8780F, and Fintek F71863FG.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12 19:08:58 +00:00
Robert Millan c1f404fc0e Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 23:41:08 +00:00
Robert Millan 39ebf2f068 Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 23:36:12 +00:00
Stefan Reinauer 3bb2628c7b Thanks to Uwe Hermann for spotting this typo.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 21:57:20 +00:00
Uwe Hermann 1ec5094390 Add support for the Winbond W83627DHG Super I/O.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 21:10:07 +00:00
Robert Millan 81af3d4a00 [PATCH] coreboot-v2: Add multiboot support
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 20:20:54 +00:00
Jordan Crouse 5cb4d9d663 [PATCH] coreinfo: Add multiboot parsing support
Rename the "coreboot" menu "firmware", and add a module to parse
the multiboot table.  For now, just parse memory, but it can be
expanded as needed.

Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 19:53:42 +00:00
Jordan Crouse 6c6e4333c4 [PATCH] Add sysinfo_have_multiboot function
Add a new infrastructure for returning system information to payloads.
First up - a pointer to the multiboot table.

Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 19:51:14 +00:00
Uwe Hermann 3b6c527322 Always enable serial before SMBus (or as early as possible), as the SMBus
enable may do printk()s which result in a 2 minute delay on some boards.

Fix this on all boards which currently do smbus_enable() before enabling
the serial console.

Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 14:26:03 +00:00
Stefan Reinauer 779b3e3129 Merge some parts of the i945 review (trivial):
* fix \r\n occurence in i945 code
* drop early TOLUD write
* fix 16bit BCTRL1 access

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10 15:43:37 +00:00
Stefan Reinauer fb9f35d36b cosmetic update for getpir.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10 13:52:14 +00:00
Uwe Hermann a163729862 i945.h: Add some more comments, align data for better readability (trivial).
Also, add missing C1DRA2 #define (as per public datasheet).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-09 10:57:26 +00:00
Carl-Daniel Hailfinger 160361a1df The POST_CODE macro had the outb() argument order backwards.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 01:51:32 +00:00
Peter Stuge f27a3eba4d flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITE
Per report from Mario Rogen. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 01:39:12 +00:00
Ulf Jordan 8c95338f35 Update bayou to use ACS_ macros for line drawing characters.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 00:58:16 +00:00
Uwe Hermann c1c207f627 Re-add "based on" lines.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:38:31 +00:00
Uwe Hermann 65ebc791c1 Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.

Build-tested with kontron/986lcd-m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:24:05 +00:00
Uwe Hermann 556801eb61 The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).

The ICH7 needs a different init code. Drop the non-working code for now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:23:05 +00:00
Carl-Daniel Hailfinger 176e88e961 The ST M25P16 chip has been confirmed to work fine for probe, read,
erase and write by Stéphan Guilloux.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-05 22:54:36 +00:00
Carl-Daniel Hailfinger aad6502d8a Add support for 8 new chips to flashrom and fix up 2 existing chips
as well.
Replace age-old TODO comments with real explanations.

Fixed chips:
Fujitsu MBM29F400TC (ID definition)
Macronix MX29F002T (chip name)

New chips:
Fujitsu MBM29F004BC
Fujitsu MBM29F004TC
Fujitsu MBM29F400BC
Macronix MX25L512
Macronix MX25L1005
Macronix MX25L2005
Macronix MX25L6405
Macronix MX29F002B

Straight from the data sheets, compile tested only.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-04 12:11:12 +00:00
Jens Rottmann 98afd9b75b Fix compile errors if CONFIG_FS_PAYLOAD=1:
Compile error in filo.c if AUTOBOOT_DELAY=0. Replace
#ifndef AUTOBOOT_DELAY
with
#if !AUTOBOOT_DELAY
which should work for both the #undef and the =0 case.

In ext2fs.c, fat.c
#if ARCH == 'i386'
results in a compile warning: "multi-character character constant" and
the condition ARCH == 'i386' is mis-evaluated as FALSE, eventually
choking the assembler on a PPC instruction. Change it to
#ifdef __i386

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 23:16:00 +00:00
Jens Rottmann 632f86515a Add the missing I/O resources for IT8712F GPIOs. (E.g. some LiPPERT
boards need them to switch the com ports from RS232 to RS485.) The PnP
resources should prevent other devices from being mapped at the same
spot, even if no OS driver actively uses them.

The IT8712F manual makes it look like PNP_IO1 had a size/granularity of
1 byte, but that must be a mistake. The Simple-I/O resource has a size
of 5 bytes (1 for each GPIO set 1-5) and trying different addresses
reveals a granularity of 8.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 22:58:56 +00:00
Marc Jones 9cc49b21f8 Set asus/a8v-3_se to use printk in CAR. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 22:46:27 +00:00
Marc Jones c87ddd91c7 Update K8 FID/VID setup. Add support for 100MHz FIDs (revG).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 21:39:03 +00:00
Jordan Crouse fbeba2313f Move the default payload to be more buildrom friendly.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 16:55:22 +00:00
Ronald G. Minnich d4ef0541db modify pirq tables for epia-cn.
Not tested, builds, derived from getpir. Definitely better than what was there. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Bari Ari <bari@onelabs.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 04:08:35 +00:00
Carl-Daniel Hailfinger 6f31f11031 Dump ICH8/ICH9/ICH10 SPI registers in flashrom.
This helps a lot if we have to track down configuration weirdnesses.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:20:22 +00:00
Carl-Daniel Hailfinger 6287e2e7aa Add additional SPI sector erase and chip erase command functions to
flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and
architecturally
more sound.

TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function
  
Thanks to Stefan for reviewing and commenting.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:02:11 +00:00
Stefan Reinauer d22ef49783 Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead.
This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 19:51:50 +00:00
Uwe Hermann 54c5276c3a Get the lzma/ directory from v3 via svn:externals, for use with Bayou.
Also, fix a few Makefiles regarding lzma stuff and 'make clean' behaviour.

Add bayou.xml.example which users can use as a starting point.

Bayou does compile fine now (if you build ../libpayload) before.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 17:48:20 +00:00
Uwe Hermann 7eb845e815 Import a slightly modified Bayou version into svn. This is based
on the last snapshot posted by Jordan Crouse. This commit is long
overdue.

Changes by me include:

 - Rename 'utils' to 'util' for consistency with our other projects.

 - Move the main code out of src/* into the top-level directory.

 - Add missing license headers to the following files:
   Makefile, pbuilder/liblar/Makefile, util/pbuilder/Makefile.

 - Dropped the util/pbuilder/lzma completely. I'm working on reusing
   the lzma/ dir from v3 via svn:externals. Alas, this also means
   that Bayou won't yet compile out of the box.

 - Coding-style and white-space fixes (indent) for all files.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 17:01:06 +00:00
Uwe Hermann 91df5619db Trim down the list of southbridges supported by the i82801xx driver
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*,
and C-ICH.

All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely
not working with this driver anyway (and there's no chance to support
them reasonably with this driver without ending up in #ifdef hell).

ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar
enough to be supported by that ICH7 driver remains to be seen.

This patch was informally acked by Stefan Reinauer
<stepan@coresystems.de> on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:33:51 +00:00
Carl-Daniel Hailfinger 8a9e23c586 Add support for the ST M50FW002 chip to flashrom. Identification only,
erase/write are not implemented.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested and
Acked-by: Elia Yehuda <z4ziggy@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:25:11 +00:00
Stefan Reinauer 3d9a12f65d inteltool 82945G/GZ/P/PL Support (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 11:11:40 +00:00
Uwe Hermann 5d7a1c844e Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.
Build-tested on kontron_986lcd_m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31 18:41:09 +00:00
Uwe Hermann 50f37b0f9b Move the nvramtool manpage to section 8 (as it's only really usable as root),
as we've done with the superiotool and flashrom manpages, too (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31 05:40:04 +00:00
Marc Jones 70c793ce28 Leave room for ROM growth and for the payload. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 22:13:51 +00:00
Marc Jones 51c7838cb0 Increased the size of the failover and normal ROM_IMAGE_SIZE so abuild will
pass with toolsets that compile larger images. (trivial)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 21:31:54 +00:00
Arne Georg Gleditsch 429d6b6692 Here's a patch towards r3690 upping the ROM size for the S2912 Fam10 target to 1M.
Both regular and abuild images have been boot tested successfully. 

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 20:17:11 +00:00
Jens Rottmann edc7ef2b76 Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board:
- PC/104+ form factor
 - AMD Geode-LX CPU/northbridge
 - AMD CS5536 southbridge
 - ITE IT8712F Super I/O

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 19:34:44 +00:00
Andriy Gapon 6a4bf9886a Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 15:41:39 +00:00
Uwe Hermann b076ced581 Mark two more chips as fully tested (trivial).
- SST SST39SF010A
 - Winbond W29C011

Tested by me on actual hardware, all operations.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 03:10:17 +00:00
Stefan Reinauer a69d1db504 Flashrom support for some Numonyx parts (M25PE)
using block erase d8 as discussed with Peter Stuge

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 22:13:20 +00:00