SMBIOS has a field to display the cache size, which is currently
set to UNKNOWN unconditionally, multiply the cache size of L1 and L2
by the number of cores.
TEST=Execute "dmidecode -t 7" to check if the cache information
is correct for Deltalake platform
Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested=On OCP Delta Lake, log level can be changed via VPD.
Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This implements the two missing registers for the CPPC Hardware
Autonomous mode (HWP) to the CPPC v2 package.
The right values can be determined via Intel SDM and the ACPI 6.3 spec.
Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version
Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt Delco <delco@chromium.org>
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which
gets used in CB:45535 and CB:45536 for CPPC entries generation.
Note: This also retrieves the VMX Kconfig and enables it by default,
like done for SKL and CNL already.
Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets
selected statically by the SoC to reflect this in menuconfig.
Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead
of relying on the devicetree option `speed_shift_enable`, that is going
to be dropped.
Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F
Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code configuring ISST (Intel SpeedShift Technology) sets the ISST
capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware
P-States), which shall be done by the OS only.
Since the capability is enabled by default (opt-out), there is nothing
to do for us in the enabled-case. Practically speaking, there is no
value at all in disabling the capability, since one can configure the
OS to not enable HWP if that is desired.
The two other bits for EPP and HWP interrupt that were set by the code
are not set anymore, too. It was tested, on three platforms so far
(CML-U, KBL-H, SKL-U), that these are set as well by default in the
MSRs reset value (0x1cc0).
To reduce complexity and duplicated code without actual benefit, this
code gets dropped. The remaining dt option will be dropped in CB:46462.
Test: Linux on Supermicro X11SSM-F detects and enables HWP:
[ 0.415017] intel_pstate: HWP enabled
Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We limited the configurability of the debug level to stages that have
a `.data` section. This is not really a requirement, because a `.bss`
section should suffice and we always have that now.
We want to make the debug level configurable early but also want to
avoid calling get_option() early, as an error therein could result
in no console output at all. Hence, we compromise and start using
get_option() from the second console init on.
TEST=Booted QEMU once with `debug_level=Debug` and once with
`debug_level=Notice`. On the second boot, most messages
vanished for all stages but the bootblock.
Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable front camera power in ramstage.
BUG=b:169170677
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
This is required to make sure the defined SMBUS_BASE address is valid
even after PCI enumeration.
Tested on Prodrive Hermes.
Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46562
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In deltalake, there's no embedded controller and BMC version is
used to represent ec version.
TEST=Build with CB:45138 and CB:46070
Execute "dmidecode -t 0" to check if the firmware version is correct
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Provide a way to get BMC revision.
Tested=On OCP Delta Lake, function can get BMC revision well.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iaaa4e8bf181a38452b53c83a762c7b648e95e643
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off
for LTE sku and only use Wifi SAR table for non-LTE sku.
BUG=b:168001586
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.
Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.
BUG=None
TEST=check with empty CBI value
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic, SRCCLKREQ1# is not connected, so disable it
for terrador and todor.
BUG=b:171278849
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
According to the schematic,SRCCLKREQ1# is not connected,so disable it
on voxel.
BUG=b:171279034
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Asurada EC is using the large packet (256B) mode, and we were
seeing lots of timeout errors on various commands.
The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
and that is too small for large packet running in 1M so we
should change EC SPI to the same value that kernel is using (3M).
BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ASL for the PCH. Initially, this only contains
soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL
may be added in the future.
Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding the blank line reduces the differences with the variant
toucan-af.
Change-Id: I58bfc99109a2df2eab54a562dc13e7bd946890d9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46716
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The message was being printed too early, possibly because it was
relocated around alongside the rest of the code.
Change-Id: I4257f6f0baa1c398aa1df9bd3274458abfaf28a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46690
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to reduce differences between Haswell and Broadwell.
Change-Id: I8d6a8ee02e24bee22f0a7b69098ea8430095ba90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Rename it, add a print and factor out refclock value into a variable.
Change-Id: I7248e0b54cd6310cf74eadc5d976a8868cf822f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46688
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MRC does not use the value of SSKPD, and will overwrite it with constant
values at the end of memory initialisation. Since coreboot does not rely
on this particular bit's value, it is safe to drop the writes to set it.
MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any
documentation or code I have access to; not even for Sandy/Ivy Bridge,
the platform where this mysterious register write originally came from.
These workarounds were copied from Sandy Bridge, but do not apply to
Haswell. They were dropped on Broadwell, so drop them for Haswell too.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorder register writes to match the locking order in Broadwell.
Tested on Asrock B85M Pro4, still boots and registers are still locked.
Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Broadwell uses a 32-bit or, so also use it on Haswell for consistency.
This has no effect because MRC already locks the memory controller down.
Tested on Asrock B85M Pro4, still boots and register is still locked.
Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Haswell System Agent BIOS Spec revision 0.6.0 indicates this
register needs to be locked, and Broadwell already locks it.
Tested on Asrock B85M Pro4, still boots and register is locked.
Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46680
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This register has a lock bit. The Haswell System Agent BIOS Spec
revision 0.6.0 indicates it needs to be set, thus set it. Note that
Broadwell already locks this register.
Tested on Asrock B85M Pro4, still boots and register is locked.
Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This register had a lock bit on Sandy Bridge, but does not on Haswell.
Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot.
Therefore, remove the write to this bit, because it has no effect.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I382a6d69233ced5af069767eb61b56741ed665be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to align Broadwell and Lynx Point.
Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45717
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Morgan Jang