Commit Graph

38199 Commits

Author SHA1 Message Date
Angel Pons 1d70a331cb sb/intel/lynxpoint/acpi/pch.asl: Drop unused lines
Change-Id: I8a3a6ac69c6ce6e074f5004df24e67d2b16905fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27 22:46:41 +00:00
Angel Pons a5768f535b cpu/intel/haswell/smmrelocate.c: Spell `CPU` in uppercase
This is to align Haswell and Broadwell.

Change-Id: I8585597a8de164fb8d3b33db0d95c3aaf3cd7afc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45711
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 22:46:31 +00:00
Angel Pons f6cf4927e2 cpu/intel/haswell/haswell_init.c: Align printk's with Broadwell
Change-Id: I09f4fc5af28b20663b87d18852d585121feaab09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27 22:45:42 +00:00
Angel Pons 51eef4ed73 soc/intel/broadwell/cpu.c: Spell `CPU` in uppercase
Change-Id: I54f96911b744f1737f7141c8a96329c95ace529d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-27 22:45:35 +00:00
Angel Pons 643c82e996 soc/intel/*/chip.h: Use `uint32_t` for `tcc_offset`
Newer platforms use an unsigned type instead of an int. Follow suit.

Change-Id: I316864d3aed203c7c2bc962772895774fbc0c8da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-27 22:45:20 +00:00
Nico Huber 666c4caccb mb/Kconfig: Drop ROM sizes below 256KiB
Not even our emulation targets can build with these anymore.

Change-Id: If108a17f824a31c375a43cb4903ee07c65217f6e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45753
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 15:31:39 +00:00
Idwer Vollering 458e7dff6d util/crossgcc: correct the spelling of what should have read 'verifying'
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I46af7a225238046f393bbc4b3a214bebc527e079
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45733
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 13:33:32 +00:00
Kyösti Mälkki a7a2784528 libpayload: Fix file permissions
Change-Id: Ibdc211d7f4ec0fbbefafb5eae4c1615c64c99280
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-27 13:12:33 +00:00
Subrata Banik aab8bb2bdf soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP,
as well as GPIO IRQ routing information and supporting ACPI ASL.

For now, add the following 5 GPIO communities and 13 GPIO groups:

Comm. 0: GPP_B, GPP_T, GPP_A
Comm. 1: GPP_S, GPP_H, GPP_D
Comm. 2: GPD
Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS
Comm. 5: GPP_R, GPP_SPI0

Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-27 03:03:25 +00:00
Subrata Banik 8ff80b269d soc/intel/common/block/acpi: Factor out common gpio_op.asl
This patch moves gpio_op.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify all methods present inside
common gpio_op.asl like GRXS, GTXS etc. are still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I248f5e66994d2f3d6b0bd398347e7cf9ae7f2cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-27 03:03:06 +00:00
Subrata Banik ed6604d1f5 soc/intel/skylake: Use GPIO state macros from intelblocks/gpio_defs.h
TEST=Able to build and boot EVE platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there
2) Verify no ACPI error seen while running 'dmesg' from console
3) abuild --timeless to ensure there are no other functional changes.

Change-Id: I02df3ddf5ad33d42d97feefb0fa366ad8c856565
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45681
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 03:02:10 +00:00
Subrata Banik eab9e86733 soc/intel/icelake: Use GPIO state macros from intelblocks/gpio_defs.h
TEST=Able to build and boot ICLRVP platform.
1) Dump and disassemble DSDT to ensure GRXS function implementation
remain unchanged prior and after this CL.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.

Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 03:01:48 +00:00
Subrata Banik 8c0dda2183 soc/intel/cannonlake: Align gpio_op.asl with TGL
Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros.

TEST=Able to build and boot CNL and CML platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.

Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 03:01:31 +00:00
Subrata Banik 1bfb74c14c soc/intel/{jsl,tgl}: Fix GRXS function to get GPIO number proper
This patch ensures that GRXS perform PAD_CFG0_RX_STATE mask first
and then right shift PAD_CFG0_RX_STATE_BIT to get correct GPIO number.

Change-Id: I96611936f70f79e9dc5ee9414ec68cef00d0d13a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-27 03:01:04 +00:00
Zoltan Baldaszti be58923fed payloads/external: add support for BOOTBOOT payload
BOOTBOOT is a multi-platform, architecture agnostic boot protocol.
The protocol describes how to boot an ELF64 or PE32+ executable inside
an initial ram disk image into clean 64 bit mode. This version uses
libpayload to do that. Depending on the lib's configuration, initrd
can be in ROM as a cbfs file or a Flashmap partition; on disk a GPT
partition or a file on a FAT formatted ESP partition.
For more information see https://gitlab.com/bztsrc/bootboot

Change-Id: I8692cde0730338026a7760a293c1e37f66004bc0
Signed-off-by: Zoltan Baldaszti <bztemail@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 23:08:07 +00:00
Kyösti Mälkki 871c8734b9 soc/intel/apollolake: Drop select SMP
The SOC has MAX_CPUS>1 so this is redundant.

Change-Id: Icb4c7551031f4e32e01198261ee9ae9b95f18142
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26 23:07:09 +00:00
Kyösti Mälkki 57550a28b8 cpu/qemu-x86: Drop select SMP
With MAX_CPUS==1, this has the effect of removing spinlock
implementation. But since is_smp_boot() evaluates false and
SMM uses separate smi_semaphore, there is no concurrency to
protect against with a spinlock.

Change-Id: I7c2ac221af78055879e7359bd03907f2416a9919
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26 23:06:50 +00:00
Kyösti Mälkki e92abdf207 mb/emulation/qemu-i440fx: Remove TRACE=y from test build
Looks like the option is generally not compatible with
garbage collections. Nothing is inlined, is_smp_boot()
no longer evaluates to constant false and thus the symbols
from secondary.S would need to be present for the build
to pass after we set SMP=n.

Change-Id: I1b76dc34b5f39d8988368f71a0a2f43d1bc4177e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43817
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-26 23:06:43 +00:00
Paul Fagerburg 96fd529a92 lib/Makefile.inc: fix name of config string
The config string is HAVE_SPD_IN_CBFS, without the "BIN".

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I728f64b2dd93b0e3947983b9b3701e185feff571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-26 19:33:49 +00:00
Patrick Rudolph 819c206742 ironlake: Fix compilation on x86_64
Use correct datasize to compile on x86_64.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-26 17:31:08 +00:00
Angel Pons a32df26ec0 arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`
Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.

Alder Lake is not yet complete, so it has been skipped for now.

Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 11:42:28 +00:00
Angel Pons 2db7790795 arch/x86: Introduce `ARCH_ALL_STAGES_X86_64`
Though only one platform uses it, this will save some redundancy.

Change-Id: Ic151efe5dd9b7c89f779ac3e10c3a045f07221d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-26 11:42:22 +00:00
Raul E Rangel 2c6fcab228 vc/amd/fsp/picasso: Update to UPD 1.0.1.3
This adds eMMC preset settings.

It also fixes some formatting and a comment.

BUG=b:159823235
TEST=Build test

Cq-Depend: chrome-internal:3251807
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 23:22:50 +00:00
Jason Glenesk bc5214342f soc/amd/picasso: Generate ACPI pstate and cstate objects in cb
Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.

BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork

Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-25 22:49:56 +00:00
Abe Levkoy ebd234e059 mb/google/volteer: Wake on AC connect and disconnect
Add AC connect and disconnect to S0ix lazy wake sources.

BUG=b:161466940
BRANCH=master
TEST=Connect and disconnect charger in S0ix; observe wake

Change-Id: I30046a379ff75c33b991e355cc8d142241ee8b2e
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45669
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 22:42:42 +00:00
Angel Pons 6fd9adbecb nb/intel/x4x/x4x.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I75723fe087ef16f74ca93f6faa4d3468d7958a5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-25 19:43:19 +00:00
Angel Pons 2a8ceefb27 nb/intel/x4x/iomap.h: Rename to memmap.h
It primarily contains definitions for MMIO windows. Also, remove
includes from files not directly using the definitions it contains.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: Id28080d9b2924463dd3720492d5e717d65fa0071
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 19:43:07 +00:00
Angel Pons 8f0b3e546a nb/intel/pineview: Place raminit definitions in raminit.h
There's no need to have implementation details in a public header.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I0bfd6ee72347249302ee073081f670b315aa40e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-25 19:42:43 +00:00
Angel Pons ac4e4b423f nb/intel/gm45/gm45.h: Clean up cosmetics
Align groups of definitions, reflow long lines and adjust whitespace.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I2969274c6b50f56994e45ada5d016504addfc13e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-25 19:41:35 +00:00
Angel Pons 9c2d15ff7f nb/intel/gm45: Drop unused `DEFAULT_HECIBAR` macro
Change-Id: I9e074689cd5a11d58b788b789654f3a3beb83a65
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-25 19:40:59 +00:00
Angel Pons 3378de12f6 nb/intel/gm45: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
There's no need to wrap these macros with casts. Removing them allows
dropping `uintptr_t` casts in other files. Changes the binary, though.

Change-Id: I1553cbeee45972d6deba8cb9969c69fceeb19574
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45432
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 19:40:44 +00:00
Ronak Kanabar e60155ff13 volteer: Create boldar variant
Create the boldar variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

Add "memory/Makefile.inc" generated by gen_part_id.go

BUG=b:162202257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_BOLDAR

Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-25 16:45:07 +00:00
Kane Chen fb2f356d89 mb/google/zork: Modify I2C3 CLK for Woomax to meet I2C specification
Modify I2C3 setting to follow I2C specification(lower than 400kHz).
Original setting:
.rise_time_ns = 125
.fall_time_ns = 37

Change to:
.rise_time_ns = 110
.fall_time_ns = 34

BUG=b:169207742
BRANCH=None
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0f0b791c3e701ebf6b336a8cb259eeb74c46af5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-25 15:09:42 +00:00
Kane Chen 4dcccc8365 mb/google/zork: Modify USB 2.0 PHY parameters for Woomax
Modify USB 2.0 PHY parameters for improve usb eye diagram.
1. USB 2.0 TypeC port0:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,

2. USB 2.0 TypeC port3:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,

BUG=b:169207729
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 15:02:07 +00:00
Subrata Banik 1861ca4bb8 soc/intel/tigerlake: Remove extra '_' from GPIO PIN name
Fix typo GPD__SLP_SUSB -> GPD_SLP_SUSB

Change-Id: I2beddb5665dc2f6a28b9c02e240b12da137c1b17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45685
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 14:35:54 +00:00
Elyes HAOUAS 3f56b87c51 Documentation/getting_started/kconfig.md: Add a note about Kconfig defaults
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.

Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-25 08:41:45 +00:00
Subrata Banik 3bcb6c7319 soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0
syntax across CNL, ICL, JSL, SKL.

TEST=Able to build and boot Hatch, EVE and ICLRVP platform.
Dump and disassemble DSDT to ensure GRXS,GTXS etc functions
implementation remain unchanged prior and after this CL.

Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 03:03:14 +00:00
Subrata Banik 8d4176109d soc/intel/{jsl,tgl}: Refactor gpio_op.asl
Also align GPMO ASL function with TGL.

Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-25 03:02:49 +00:00
Huayang Duan 63ee16075e soc/mediatek/mt8183: Enable CA perbit mechanism
LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.

BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 01:33:11 +00:00
Michael Niewöhner 92c1546c01 mb/clevo/cml-u: remove the duplicate WiFi PCIe device in devicetree
Change-Id: Ibb46bbf0c889bb8b3fd1a4c0331dc719baffc7a2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45678
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 00:29:53 +00:00
Felix Singer 44df56edce mb/clevo: Rename l140cu to cml-u
In addition to CB:45664, rename clevo/l140cu to clevo/cml-u being able
to add more variants under a generic mainboard later.

Change-Id: I9c16e24830ebb80752df302aa2e63d9df8edad95
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45665
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25 00:28:37 +00:00
Felix Singer 1f4b3cdeb0 mb/clevo/l140cu: Make usage of variant mechanism
Clevo mainboards can be grouped by their common platform. Therefore,
restructure the mainboard directory as a first step, so that the variant
mechanism is used.

This moves most of the code into the variant dir, since the L140CU is
the only variant at the moment.

Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 23:35:13 +00:00
Angel Pons a25eaffb69 soc/intel/alderlake: Select ACPI_INTEL_HARDWARE_SLEEP_VALUES
This resolves a Kconfig warning regarding unmet dependencies.

Change-Id: I9e70a4d333afefcb27c097aa9ce84e5effc0d7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24 18:59:39 +00:00
Michael Niewöhner 733c462c13 soc/intel/cnl: drop lpit.asl in favor of common version
Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.

The only difference between the two is the usage on macros in common
code instead of plain integer values.

Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-24 18:55:19 +00:00
John Zhao c8e309779f mb/google/volteer: Enable CnviBtAudioOffload
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.

BUG=b:169045123
TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP
configuration. Booted up to kernel on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naveen M <naveen.m@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24 18:48:56 +00:00
John Zhao c16fc8a49c soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffload
This change adds configuration support for both of CnviBtCore and
CnviBtAudioOffload.

BUG=b:169045123
TEST=Built and boot up to kernel on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Id4bf41f07c4a53de17e9eb91a8ddfb1083cbf83e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45585
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Naveen M <naveen.m@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 18:48:44 +00:00
Sheng-Liang Pan 7626e4b3ae mb/google/volteer/var/voxel: Update gpio settings for EVT
Based on EVT schematic and gpio table of voxel, update gpio settings for
voxel EVT.

BUG=b:156841729
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Idf88d83ad6d873283eb1eb8a45459ae3e74df124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45173
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 18:37:20 +00:00
Paul Fagerburg 39dbb86bbe templates: add ddr4-spd-empty.hex to SPD_SOURCES
We need at least one SPD in SPD_SOURCES when creating a new variant
of trembyle or dalboz, or else coreboot won't build. Add the empty
DDR4 SPD so that we can build the new variant.
Add an empty mem_parts_used.txt so that the developer can add the
supported memory parts and regenerate spd/Makefile.inc using
spd_tools.

BUG=b:169199396
TEST=create a new variant of dalboz or trembyle and observe that
the build succeeds.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I764690c76529780186d0a1d156a623821f9d6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-09-24 15:29:50 +00:00
Maxim Polyakov 0c5dd9febb soc/intel/common/smbus: Add support for Apollo Lake SoC
Previously, SMBUS support was not required for Apollo Lake, since the
SPD was read inside FSP-M, during memory initialization. However, the
Kontron mAL-10 COMe module contains Nuvoton HWM chip that is connected
to the processor via SMBUS. This patch adds SMBUS common driver support
for Apollo Lake to initialize this HWM.

TEST = After loading the nct7802 module on the Kontron mAL-10 with Linux
       OS, we can read the hwm registers, see temperature and fan speed:

coretemp-isa-0000
Adapter: ISA adapter
Package id 0:  +52.0°C  (high = +110.0°C, crit = +110.0°C)
Core 0:        +52.0°C  (high = +110.0°C, crit = +110.0°C)
Core 1:        +52.0°C  (high = +110.0°C, crit = +110.0°C)
Core 2:        +53.0°C  (high = +110.0°C, crit = +110.0°C)
Core 3:        +53.0°C  (high = +110.0°C, crit = +110.0°C)

nct7802-i2c-0-2e
Adapter: SMBus CMI adapter cmi
in0:          +3.35 V  (min =  +0.00 V, max =  +4.09 V)
in1:          +1.92 V
in3:          +1.21 V  (min =  +0.00 V, max =  +2.05 V)
in4:          +1.68 V  (min =  +0.00 V, max =  +2.05 V)
fan1:           0 RPM  (min =    0 RPM)
fan2:        1729 RPM  (min =    0 RPM)
fan3:           0 RPM  (min =    0 RPM)
temp1:        +53.5°C  (low  =  +0.0°C, high = +85.0°C)
                       (crit = +100.0°C)  sensor = thermistor
temp4:        +53.0°C  (low  =  +0.0°C, high = +85.0°C)
                       (crit = +100.0°C)
temp6:         +0.0°C

Change-Id: I408ef84ede27a45fb057e22b2757fa6e66277ddd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44475
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24 11:52:00 +00:00
Felix Singer da3375ed41 mb: Copy system76/lemp9 to clevo/l140cu
Copy system76/lemp9 to clevo/l140cu, since it's a Clevo notebook
actually and both have the same mainboard.

This commit is meant to create a working copy for clevo/l140cu. The only
changes are names. Further patches will follow to make this mainboard
more generic.

Since system76/lemp9 is based on System76's EC firmware, EC stuff does
not work correctly yet. This will be fixed in another patch.

Tested on TUXEDO InfinityBook S 14 v5 and PCZ Lafité Pro 14.

Change-Id: I7c2993256fd9123a8013df5ba8292ea1ead10f74
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-24 06:19:12 +00:00