Update the shared AGESA headers to 1.3.0.9.
This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated
to the same version.
BUG=b:72679320
TEST=build and boot Grunt
Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The HeapAllocateBuffer and HeapDeallocateBuffer functions are not used.
Change-Id: I491a796d87afd0e37051f9caabfff3f70d4d803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/22069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that the AGESA binary is split into two sections load the
post-memory AGESA binary into ram. It needs to be an rmdoule
so that it can be relocated into ram.
agesawrapper_amdinitenv() entry
CBFS: 'VBOOT' located CBFS at [10000:cfd40)
CBFS: Locating 'AGESA_POST_MEM'
CBFS: Found @ offset 875c0 size 11c5e
Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes)
Loading module at c7580000 with entry c7580000. filesize: 0x2bafc
memsize: 0x2bb0d
Processing 1112 relocs. Offset value of 0xc7780000
AGESA call 00020001 using c75818fe
AGESA call 00020003 using c75818fe
Fch OEM config in INIT ENV Done
agesawrapper_amdinitenv() returned AGESA_SUCCESS
BUG=b:68141063,b:70714803
TEST=Booted kahlee.
Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).
This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.
BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.
Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.
BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
noted each instance in Chrome OS build was relocated.
Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Ensure that soc/amd/common/blocks/include is the only #include
path for the AMD common code. This removes the duplicate soc/amd/common
include as well using the correct #include header in AGESA.c.
BUG=b:69262110
Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.
BUG=b:70401101
TEST=Booted and noted only one lookup per stage.
Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Make sure that AGESA headers don't get pulled directly into coreboot
files again.
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee; Include AGESA.h into files
verify that the build fails.
Change-Id: I8d6d94872ebf76a9df2850ed0452cf6b1a446ffd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy the two headers used by the Stoney BinaryPI implementation into
the 00670F00 directory so that any changes that are made to them don't
affect other platforms.
BUG=b:67299330
TEST=Build
Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into
the build, so it's obviously not needed.
BUG=b:69220826
TEST=Build
Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot doesn't need AGESA's version of Filecode.h. Some of the files
that have been copied from AGESA include the header, so we can't get rid
of it completely yet.
- Remove includes from files that weren't copied from the AGESA source.
- Remove FILECODE definitions from coreboot source.
BUG=B:69220826
TEST=Build Gardenia; Build & boot Kahlee.
Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and
update the 00670F00 Makefile to use it instead of using the common
version.
This allows changes to stoney without affecting the rest of the AMD
binary PI platforms.
BUG=b:67299330
TEST=Build Gardenia; Build & boot kahlee
Change-Id: I2fe4303f882938e9d917a3001476213f49426455
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Create header files for the stoneyridge PI that pulls in AGESA pi
headers and encloses them in #pragma pack push/pop to keep the
'#pragma pack(1)' in Porting.h from leaking.
- Add that header to agesawrapper.h, replacing AGESA.h and Porting.h
Following patches will update the coreboot code to use only
agesawrapper.h to pull in the AGESA headers.
BUG=b:66818758
TEST=Build tested
Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ModuleIdentifier must be 8 bytes. Every other location else that uses
this value explicityly defines it as 8 bytes. If it's initialized here
to less than 8 bytes, it gets passed to those other locations with
garbage at the end and fails to load the AGESA binary.
TEST=Build & boot Kahlee
BUG=B:69165234
Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These functions are not currently used, and were not in the original
AGESA source code drop.
The structs involved here were marked "private" in AGESA headerfiles
and should not be exposed. They could be handled as anonymous structs
and required allocation size is communicated by other means.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: Iec346205470150257fd9d09131d54231b321740b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.
Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The HeapAllocateBuffer and HEAPDeallocateBuffer functions are not used
in Stoney Ridge, so get rid of them.
Change-Id: I716d5c8957ced52c25fd501697111b1b0b263467
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Half the files were being placed in build/agesa and half in
build/libagesa.
Change-Id: Ied69dafffe2eb3354bd430789e098a1cb1d40551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It was either SAGE or AMD AES who implemented these for
binaryPI, and it is not part of the documented AGESA API.
My conclusions of these are:
AmdGetValue() returns values from build-time configuration,
these may not reflect the actual run-time configuration as
there are OEM customization hooks to implement overrides.
AmdSetValue() in __PRE_RAM__ will fail, as configuration
data is const. Also AmdSetValue() in ramstage may fail, if
said configuration data has already been evaluated.
Semamtics of these calls are unusable unless one also has
access to PI source to make exact decision on when they
can be called. Remove these now that stoneyridge does not
actually require them.
Change-Id: I3379a75ce3b9448c17ef00eb16d3193c296626cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change the cache-as-ram teardown to use invd instead of wbinvd.
Save the return and recover the call's return address in
chipset_teardown_car.
CAR teardown had been modified to use wbinvd to send CAR contents
to DRAM backing prior to teardown. This allowed CAR variables,
stack, and local variables to be preserved while running the
AMD_DISABLE_STACK macro.
Using the wbinvd instruction has the side effect of sending all
dirty cache contents to DRAM and not only our CAR data. This
would likely cause corruption, e.g. during S3 resume.
Stoney Ridge now uses a postcar stage and this is no longer a
requirement.
BUG=b:64768556
Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20967
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.
AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.
Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.
We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.
Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This file mostly mimics Porting.h and should be removed.
For now, move it and use it consistently with incorrect form
as #include "cbtypes.h".
Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression of IDS debugging after commit
1210026 AGESA buildsystem: Reduce include path exposure
Mainboard directory was removed from libagesa includes
path here, and this resulted with fam15tn and fam16kb using
a template OptionsIds.h file under vendorcode/ instead.
Add mainboard directory back to include path of libagesa
and remove those (empty) template files.
Change-Id: Iee4341a527b4c152269565cac85e52db44503ea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's already implemented like this with binaryPI API header.
That implementation is essentially the same with 'const' qualifier
just being ignored in the build process for PI blob.
For open-source AGESA build, work around -Werror=discarded-qualifier
using a simple but ugly cast.
Change-Id: Ib84eb9aa40f1f4442f7aeaa8c15f6f1cbc6ca295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
One liner that fixes a warning with clang
Change-Id: I4d7dfaa5fcf0e95acd650e4c129e0899b5d68f09
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
AGESA internal headerfiles are allover the place. Luckily, they
have unique names within the Proc/ tree so include every existing
directory in undefined order.
Change-Id: I86f080e514391a3f0f05d379d24d490ce075060e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
We never had a board in the tree that implements this.
If you are interested in implementing such board, note
that also f12 and f14 had copies of the same refcode.
As part of the sourcetree cleanup it was not studied
which was the most up-to-date one for AM3r2.
Change-Id: Ic7dd065c0df08c22af6f3a2dcfc7ff47d6283a46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
