Define a new field in the board config EEPROM layout for port B Vref.
Write port B Vref settings to unused non-volatile NID 0x12 instead of
NID 0x18, the actual port B NID. Because per-port Vref settings don't
persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
to restore port B Vref after resetting the codec.
Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use lowercase for hex numbers, sort includes alphabetically and avoid
relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead
of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one
definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up
the indentation of some includes.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There's no need to use a variant structure here. Only one variant is
used, and revision-specific differences are handled at run-time, and
it's unlikely that another variant will ever exist.
Reorganize the mainboard code to get rid of the variant structure.
Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID
straps and Developer Mode Beep signals. During boot up it is LOW and
selects RAM_ID straps. When the system enters OS, it is driven HIGH and
selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5
domain it does not reset until the system enters mechanical off (G3)
state. On scenarios where the power button is pressed when the system is
in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still
selecting DEV BEEP signal. This causes boot up failures. Fix this by
configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage.
BUG=b:204450368
TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle
followed by a S5 -> S0 boot cycle for 2 iterations successfully.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn on the LAN device in devicetree and add Kconfig item
RT8168_GET_MAC_FROM_VPD to support programming MAC address.
BUG=b:193750191
BRANCH=None
TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD.
Use 'ifconfig' to check if the MAC written successfully.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207625007
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the beadrix variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:204882915
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BEADRIX
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
In next build phase, primus will exchange i2c port for touchscreen and cr50.
BUG=b:207834727
TEST=build pass
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the taniks variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:207402720
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TANIKS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55
and Intel's doc #626774.
2. Set PsysPL2 and PsysPmax according to the conclusion in issue
b:193864533 comment#23 and comment#29.
BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Copy function variant_update_power_limits from brya to set power limits.
Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and configure the psys power limits.
BUG=b:193864533
BRANCH=none
TEST=Build pass
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap
TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C,
need change I2C map, sch amd GPIO map. b/196293623
BUG=b:207613972
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after
exiting S0ix suspend states.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:141191727
TEST=built a guybrush firmware image and verified that the RO_GSCVD
area was indeed added:
$ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \
grep -B3 RO_GSCVD
area: 25
area_offset: 0x00808000
area_size: 0x00002000 (8192)
area_name: RO_GSCVD
$
- verified that guybrush device boots fine with the new image.
Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ChromeOS kernel platform driver is adding support for a ChromeOS
privacy screen device, and in order to locate that device, the driver
uses the GOOG0010 reserved HID for this.
Patch for 5.10 kernel can be found at:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984
BUG=b:206850071
TEST=dump SSDT, see _HID instead of _ADR
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some herobrine variants have USB hub powered by discrete LDO that is
controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
BlueTooth disappeared after disabled USB2 port 9,
so we need to re-enable it.
BUG=none
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7971509d7428562c80e781339ead059a189cea13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fork multiple "4ES" variants off some brya devices to
properly support ES SoC.
BRANCH=none
BUG=b:201767461
TEST=emerge-brya coreboot and check the artifacts
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There are no quad-core CPU models with fam14, \_SB.C002 and .C003 get
removed from ASL.
Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.
There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.
Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The section is the same and at root scope.
Change-Id: I3b3ff2fddc7d4db09903151bcb92e3e1b5dc7d69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Dumped using inteltool from the Dell BIOS version A30.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no support for SD card on Corsola reference board, so
we add a configuration to disable SD card initialization to
prevent setting GPIOs in a mistaken way.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Kano EVT will exchange i2c port for touchscreen and cr50.
BUG=b:195853169
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In different sku, some unused GPIO pins are processed by NC for power
consumption.
BUG=b:196790249
TEST=emerge-brya coreboot chromeos-bootimage and check power
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enabling crashlog helps partners to debug hang issues efficiently.
BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in
depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble
Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
At present the default ROM for for QEMU is too small for U-Boot to fit.
Add a condition to catch this and expand it to a 1MB ROM. This allows
booting U-Boot under emulation.
It also matches the size used by other emulation boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ia1a8c1109e3ece5fec56255173a2d19d4a130bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were verified by the thermal team.
BUG=b:207463762
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update thermal setting from thermal team.
BUG=b:205648035
TEST=build and verified by thermal team.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If5082462b79c88ecf510f7a552381c792604366e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Set power limits for kano based on CPU SKUs.
BUG=b:205648035
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble.
BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.
On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.
Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.
Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210
Ethernet NIC, but their numbering isn't consistent with the PCIe root
port function numbers. With only a M.2 SSD plugged in, Linux uses the
following names:
PHY 0 ---> enp6s0
PHY 1 ---> enp4s0
PHY 2 ---> enp3s0
PHY 3 ---> enp1s0
PHY 4 ---> enp2s0
These names change after adding or removing PCIe devices in slots
connected to root ports that get enumerated before the NICs' root
ports, because the assignment of secondary bus numbers depends on
the enumeration order. Because of this, the "predictable" network
interface names are not at all predictable, which is awful.
To avoid this, describe the NICs using SMBIOS Type41 entries with the
correct instance numbers. With this patch, Linux uses these names:
PHY 0 ---> eno0
PHY 1 ---> eno1
PHY 2 ---> eno2
PHY 3 ---> eno3
PHY 4 ---> eno4
No matter what PCIe devices are present, these names don't change.
Change-Id: I7a527298f84172f9135006083ad7e748dcc27911
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
