Mendocino only has 4 PCIe lanes exposed, so there's no need for 6
PCIe functions to control them. These functions just show up as
leftover devicetree devices.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b801d82f085d77706b8053a8fc9728101f155e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Resolve this message:
[INFO ] PCI: Static device PCI: 00:16.3 not found, disabling it.
The ME KT is very unlikely to exist on a consumer device as it is only
used in combination with Intel AMT. AMT comes only with the corporate
ME variant, whilst this mainboard is consumer grade.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I15dd586db9cb4b2dd615b7bf78665df86a32cb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73829
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
We're not going to move the AMDFW binary around at this point, so get
rid of the TODO.
BUG=None
TEST=None
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If802c3ee19f4e6a3a74da49bbda55f6a89fa8060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73827
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Because Mendocino doesn't support PCIe Gen4, PSPP on this platform does
not save any power, so leave it disabled.
BUG=273889287
TEST=None
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1a1c6692cd0a44469a35582042b92eeec31073fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since commit 2f6b7d557d ("amdfwtool: Move the filling of table headers
into functions"), the combo_psp_directory union element in the
embedded_firmware is unused and the new_psp_directory element is used in
all places, so replace the union of new_psp_directory and
combo_psp_directory with just the new_psp_directory struct element.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Replace the legacy ACPI Processor() object as it only
supports 8bit IDs and thus no more than 255 cores. Use the
new ACPI Device() object that supports more than 255 cores.
Test:
- Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running
384 CPU cores in total.
- Verified on Intel ADL RVP with 20 cores that Linux 5.15 is
still working without errors.
Change-Id: I309c06b6824704c84fd16534655334a6f269904a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Intel Client PCIe* controller expects each device should drive the
SRCCLKREQ#. If the GPIO is set to native mode for a device, which does
not support SRCCLKREQ#, then during RTD3 exit link would not be
established. Because controller samples the SRCCLKREQ# before
detecting the device and break L1 as the system might enter L1SS as
controller detects SRCCLKREQ# as de-asserted.
As a workaround the Pins must not be configured in Native Mode (CLKREQ
native function). Therefore here they are not configured at all.
source: 689882 (intel document ID)
So apparently hardware doesn't sample SRCCLKREQ Pin if it's not
configured as such.
That workaround suggestion however also brought a patch to FSP, which
in turn causes the same bug (even if SRCLKREQ are not configured).
Usually in order to make use of root port power saving features (e.g.
clock gating), the Root port must either be disabled or a CLKREQ Pin
must be configured. The patch however removed that check before
enabling power management for the rootport.
Workaround (until FSP is fixed):
pretend to FSP that the rootports have a CLKREQ Pin attached, by
supplying them in the FSP UPDs. That will cause FSP to configure the
CLKREQ Pin and enable power management for said rootport, but it will
not crash on L1 entry/exit. That has been done on the Atlas board
(as workaround) for a short period of time (before applying FSP Fix)
like this:
// RP 5 (the rootport you want to fix)
- memupd->FspmConfig.PcieClkSrcUsage[2] = 4;
// e.g. choose a clkreq pin that is not routed out
- memupd->FspmConfig.PcieClkSrcClkReq[2] = 0;
Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent
the same issue, but for CPU root ports. If not done the following will
happen in coreboot:
[DEBUG] PCI: 00:06.2 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:06.2
[DEBUG] PCI: pci_scan_bus for bus 02
[DEBUG] PCI: 02:00.0 [1344/5410] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
[INFO ] PCIE CLK PM is not supported by endpoint
[INFO ] ASPM: Enabled L1
[EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting
[EMERG] Code: 0 eflags: 00000046 cr2: 00000000
[EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000
[EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100
[EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56
[EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If2acdc16f37cdae0292f55d210b058f82179bfb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The ADL RVP has an i219 PHY connected to the PCH internal MAC.
Enable it to have working ethernet on the board.
Test:
Added GBE region and verified that the PCI device 00:1f.6 is working.
Change-Id: I2ca1af00ae4564a04f5388cd3734bb735d87352e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Due to a non-optimal RX signal (receive) on PCIe root port #4 (00:1c.3)
and #5 (00:1c.4), the speed must be limit to Gen 1.
BUG=none
TEST=RX signal measured with oscilloscope
Change-Id: I695c0ef961290676fe421b6efd631d6e94d6d556
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73767
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In cases where there are limitations on the connected device behind the
PCIe root port it can be necessary to limit the speed. The FSP parameter
'PcieRpPcieSpeed' allows to set the speed limit.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the
vr_config table.
Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs and use this
bitfield struct in get_pstate_core_freq and get_pstate_core_power. The
signature of those two function will be changed in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic489b8e1332dde2511647c065ccbdef541bcbcc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs and use this
bitfield struct in get_pstate_core_freq and get_pstate_core_power. The
signature of those two function will be changed in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If92a4773c669ac2df45396eee52f6de780adbdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add the pstate_msr union of a bitfield struct and a raw uint64_t to
allow easier access of the bitfields of the P state MSRs and use this
bitfield struct in get_pstate_core_freq and get_pstate_core_power. The
signature of those two function will be changed in a follow-up commit.
TEST=The coreboot-generated SSDT containing the P state packages stays
identical on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8dc293351f9941cfb8a9c84d9fb9a4fd76361d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
[ERROR] PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree
[ERROR] PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree
Set them to zero. This is also what the values are set to using vendor
firmware 1.90.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ide5980224f042e3da289aa28a18042ee8505d943
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73812
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Resolve this message:
[INFO ] PCI: Static device PCI: 00:16.3 not found, disabling it.
The ME KT is very unlikely to exist on a consumer device as it is only
used in combination with Intel AMT. AMT comes only with the corporate
ME variant, whilst this mainboard is consumer grade.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ie1f0bad276f5c124d8d52772330982bf1342c72e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.
TEST=Able to build and boot google/rex. GPIO debug print is showing
GPIO PAD config DW1 bit[14:17] are getting programmed.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Provide support function to query fsp misc_data hob and return smu
reported power and thermal limit.
BUG=b:253301653
TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in
the hob.
Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b
Signed-off-by: Jason Glenesk <jason.glenesk@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enable_gpio for USB power resource
BUG=b:273891168
TEST=Able to detect USB CAM
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I08ebe560c8b75c8b590c889b7b90dbe678318d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Follow thermal team's request on b/248086651 comment#32. Update the
thermal table setting for each mode and the conditions of temperature
switching.
BUG=b:248086651,b:241180483
TEST=emerge-skyrim coreboot
Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.
Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.
Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch modifies the serial msg log_level at runtime to highlight
an ERROR if the DIMM count is zero. It would help to draw the
attention while parsing the serial msg and catch any underlying issue.
TEST=Able to see ERROR msg while booting google/rex with FSP v3064
Without this patch:
[DEBUG] 0 DIMMs found
With this patch:
[ERROR] No DIMMs found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some MSRs used in SPR code are common among currently supported
Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs
which have changed are added to SPR's soc_msr.h.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
The current VBT causes problems with Windows 10. Once the Intel driver
is used instead of the generic graphics driver, the display turns off
although the system keeps running normally. Linux has no issues. It had
been extracted from the vendor video BIOS, which in turn had been
extracted from the vendor firmware.
This change replaces the VBT with one that was dumped through debugfs
and the drm/i915 driver in Linux, booted from the vendor firmware at
version 2.10 (beta). It fixes the issue with the Intel graphics driver
on Windows 10.
Change-Id: Icbb3950b37dad5ed308f3bafb73b71859227d26b
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73711
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the NixOS configuration into a subdirectory so that configurations
for other distros can be added as well.
Change-Id: I0462c1a6541878c973be4302c5c5e9e9bfaed2a6
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Certain C source files for coreboot stages require fmap_config.h to
be present. When building coreboot using multiple jobs the dependency
is not always satisfied due to race condition and results in make
error. Work around it by adding fmap_config.h to stage C deps.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a70beedf2eb1c018c5ff98163904253f9a87a61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69819
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Updating from commit id 9881bb93a:
2022-11-21 19:12:00 +0100 - (Merge "docs(spm): update threat model" into integration)
to commit id 4c985e867:
2023-03-14 19:53:19 +0100 - (Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integration)
This brings in 547 new commits.
Note: commit id 1f49db5f solves the "LOAD segment with RWX permissions"
error when binutils 2.39 is used.
Change-Id: I35355040c6958d470d78002048e78a06fd7f6f02
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73735
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HSPHY firmware must be downloaded to DMA-allowed host address
space. Check for DMA buffer presence and use it as the buffer for HSPHY
firmware to be downloaded from CSME.
TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4
with DMA protection enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new common block with VT-d/IOMMU support. The patch adds an
option to enable DMA protection with PMR. However the payload and
OS must support VT-d in order to properly handle I/O devices.
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This patch updates the Memory Hob Info data structure as per FSP
v3064 source code change.
BUG=b:273894357
TEST=Able to see `smbios type 17` table while booting google/rex.
Without this patch:
[DEBUG] 0 DIMM found
With this patch:
[DEBUG] 8 DIMM found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56BK7BX068 1 (0001)
MT62F1G32D2DS-026 WT:B 1 (0001)
K3KL8L80CM-MGCT 1 (0001)
H58G66BK7BX067 2 (0010)
MT62F2G32D4DS-026 WT:B 2 (0010)
K3KL9L90CM-MGCT 2 (0010)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id
Change-Id: I82919919ec33d6bf9d86132490df754873b5df88
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch passes a hint flag to QcLib on Lazor boards to tell it to
limit the DDR frequency for certain memory parts (8GB Hynix) to work
around a board-specific stability issue.
BRANCH=trogdor
BUG=b:267387867
TEST=Validated on qualcomm sc7180 development board
Change-Id: I45915cf93d2a57ff0c9710f2ac36dfb665eff1c6
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Create the yavilla variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVILLA
Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add new memory MT62F2G32D4DS-026 WT:B to replace H9JCNNNBK3MLYR-N6E．
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-026 WT:B 2 (0010)
MT62F2G32D4DS-026 WT:B 3 (0011)
K3LKBKB0BM-MGCP 4 (0100)
BUG=b:273177939
BRANCH=None
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I545bd8d9f88e7b3055acef4066769e6fcb766cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73681
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print IOAPIC ID for GSI #0 in logs, as part of IOAPIC initialization.
BUG=None
TEST=Confirmed "IOAPIC: ID = 0x00" printed in logs.
Signed-off-by: Jay Patel <jay2.patel@intel.com>
Change-Id: I8d8e94fe623795d059ec2abbb3319b60fd80f5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Rwmove temp sensor 3 for taniks since we do not use it.
BUG=b:265075696
TEST=emerge-brya coreboot, flash to DUT and will not see error messages
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I9e83a3ac56d5c42d8d6839cc4d961adf0b656fb5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73725
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch will add new board variant to enable MCHP1727 EC Card
for MTL-RVP
BUG=b:262800416
BRANCH=none
TEST=check if you can observe MEC EC option as part of make menuconfig.
Able to boot to ChromeOS with Microchip EC.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie0d3c37bcab5e4b90a131e17996c4b6dcbae7d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Martin Roth