Commit Graph

42928 Commits

Author SHA1 Message Date
John Zhao 270e25594f soc/intel/alderlake: Avoid NULL pointer deference
Coverity detects dereference pointers req and res that are NULL when
calling the pmc_send_ipc_cmd function. This change prevents NULL
pointers dereference.

Found-by: Coverity CID 1458077, 1458078
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:47:53 +00:00
Sumeet Pawnikar f96aa7a687 IMOK: Add IMOK method support for DPTF
Add IMOK method support for DPTF

BRANCH=None
BUG=b:187797417
TEST=Built and tested on dedede board

Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:47:25 +00:00
stanley.wu 6142a989a1 mb/google/dedede/var/boten: Modify Wifi-SAR sku condition
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR
detect condition for boten/botenflex sku.

BUG=b:186174768
TEST=build and test on boten/botenflex

Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07 14:59:16 +00:00
Tao Xia 5aa511931f mb/google/dedede/var/storo: Update DPTF parameters
Update DPTF parameters from internal thermal team.

BUG=b:180875582
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07 14:58:17 +00:00
Tao Xia 6c1bdc8939 mb/google/dedede/var/sasukette: Configure I2C times for touchpad
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.

Measured I2C frequency just as below after tuning:
touchpad:390.4 kHz

BUG=b:192601250
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-07 14:57:43 +00:00
Werner Zeh ae6a3e83ca mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and
provide a flashmap for partitioning. Select the used flashmap on variant
level to allow different layouts for different variants.

Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07 14:56:54 +00:00
Werner Zeh f2c9813656 mb/siemens/mc_ehl: Clean up Kconfig
Remove Kconfig switches that are not needed for mc_ehl based mainboards.

Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-07 14:56:15 +00:00
Jan Tatje b7eec4a844 util/ifdtool: Add sklkbl to IFDv2 platforms
Currently ifdtool breaks the descriptor because it treats it as IFDv1.
This change adds it to the list of IFDv2 platforms.
Fixes boot for X11SSH-LN4F.

Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07 14:55:40 +00:00
Iru Cai 88eb167868 arch/x86: Save resume vector to stack in x86_64 mode
In x86_64, the first function parameter is passed in rdi register, and
the 32-bit code after exiting long mode reads the resume vector in
4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp).

Also note that the function attribute "regparm" only works on x86-32
targets according to the GCC manual, so "asmlinkage" doesn't change
the ABI of an x86_64 function.

Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64
mode after this change.

Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55947
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07 14:54:56 +00:00
Arthur Heymans d109354c0f Makefile.inc: Drop the cbfs master header from non-X86
The pointer to the header has a x86 top mmaped address even though the
boot medium is not mapped that way. If no pointer is used to find the
header FMAP is needed. If FMAP is used anyway there is no need for a
cbfs master header.

Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07 14:52:10 +00:00
Arthur Heymans 95761c573a Makefile.inc: Fix IFITTOOL dependencies
Add IFITTOOL as a dependency where needed and remove where it is
unneeded.

Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07 14:51:22 +00:00
Arthur Heymans e3c03d7f33 Makefile.inc: Remove explicit ramstage dependency for coreboot.rom
This is already handled in $(prebuild-files).

Change-Id: I648f97198772d30d6d267ab9d6f7fa8d1d5d0e91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07 14:50:54 +00:00
Ryan Chuang 54a2a0ad45 vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07 14:49:34 +00:00
Ryan Chuang c6ed254835 vc/mediatek/mt8195: Improve settings of duty calibration
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07 14:49:15 +00:00
Ryan Chuang e53cbfdbf4 soc/mediatek/mt8195: Add dramc_param.h
The dramc_param.h defines the header version,
structure and APIs for the DRAM calibration parameters
stored on the flash, and should be platform independent.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07 14:47:42 +00:00
Garmin Chang 6615c2d08c soc/mediatek/mt8195: Enable DCM
Enable DCM settings on the MT8195 platform.
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-07 14:47:21 +00:00
Kane Chen 4ceaf46423 mb/google/zork/var/shuboz: adjust telemetry settings
According to stardust test tracking report to adjust
telemetry setting.

VDD Slope : 30595 -> 30400
VDD Offset: 77   -> 317
SOC Slope : 24063 -> 23789
SOC Offset: 105   -> 94

BUG=b:190338440
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2021-07-07 09:27:14 +00:00
Patrick Rudolph c439e07936 cpu/intel/car/core2/cache_as_ram: Add x86_64 support
Tested on Lenovo T500 with additional patches.

Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-07 05:49:10 +00:00
Patrick Rudolph 6edaa21698 ironlake: Add support for x86_64
Allow to compile the experimental x86_64 code.

Tested on Lenovo Thinkpad T410.
Hangs in SMM relocation. When skipped boots into GNU/Linux.

Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-07-07 05:49:01 +00:00
Angel Pons 3ac1f21c7a configs: Explicitly specify vendor and mainboard
Relying on the implicit defaults for these settings can cause issues in
the future. For example, commit 8cc4c5a1e7
(config.dell_optiplex_9010_sff: Specify board model) was done to prevent
a build failure when adding support for other Dell mainboards which make
the default board change.

Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56079
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-07 05:48:25 +00:00
Aamir Bohra af343cff76 soc/amd/picasso: Allow end range entry for max device ID in IVRS
Allow hot plug devices to subscribe to IOMMU services. Currently the
IOMMU end range is limited to device B:0 D:1f F:6. This prevents the
devices on bus 1 and higher to subscribe to IOMMU services. As per AMD
IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined,
whether the device ID is actually populated or not. Device entries are
used to report ranges when hot-plug and SR-IOV devices are possible.
With this change the hot plug devices can now bind to IOMMU services
(as tested on kernel v5.4), and below errors are not seen in dmesg.

AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000]

AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000]

AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000]

TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen.
      The hot plug devices can successfully bind to IOMMU services in
      kernel.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: I256c0f8032662674a4d75746de49c250e341c579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06 22:10:10 +00:00
Arthur Heymans 0a71934585 configs/config.foxconn_g41m: Build test with X86_64
Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56042
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06 06:11:50 +00:00
Arthur Heymans d7461f1e4b nb/intel/x4x: Expose x86_64 support
TESTED on foxconn g41m.

Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56022
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06 06:09:48 +00:00
Arthur Heymans 8a6053b2bf cpu/intel/car/p4: Add x86_64 support
Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-06 06:09:37 +00:00
Patrick Rudolph adcf7827bd arch/x86: Use ENV_X86_64 instead of _x86_64_
Tested on Intel Sandybridge x86_64 and x86_32.

Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-06 06:09:13 +00:00
Patrick Rudolph e85e7af6d0 configs: Build test x86_64 on Sandy Bridge
Add defconfig to build test x86_64 code on Sandy Bridge.

Change-Id: I2c18af8bfa87636c68741e4759059276c287d052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrik Tesarik <depate@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-05 16:49:22 +00:00
Werner Zeh c4d110afde mb/siemens/mc_ehl: Provide a proper scheme for variants
There will be more variants of this mainboard so prepare the scheme for
Kconfig to handle the variants properly.

Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05 10:53:16 +00:00
Werner Zeh e5a1fc788f mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb
Add a new mainboard called mc_ehl which is based on Intel's
'elkhartlake_crb'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Follow-up commits will
introduce the needed changes for the new mainboard.

Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-05 10:52:53 +00:00
Angel Pons d19cc1119f device: Reflow strings in printk statements
To ease finding some log messages, reflow their strings to use one line.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-05 10:52:19 +00:00
Varshit B Pandya a932a471cc mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for camera ACPI
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.

TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05 10:51:43 +00:00
Varshit B Pandya 048870ae2c mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ACPI
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.

TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Compared SSDT with this patch against DSDT without this patch, they are same

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-07-05 10:51:32 +00:00
Paul Menzel adface7ace util/board_status: Do not display grep message
Redirect stdout and stderr from grep to check for unknown timestamps,
when no timestamps are stored, which is already logged earlier.

    Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring
    Getting remote dmesg
    grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory

Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-05 10:51:12 +00:00
Karthikeyan Ramasubramanian bb87552c98 mb/google/dedede: Fix the pointer/address used in memcpy
The caller is already passing the address to the required LTE reset and
enable GPIO. During memcpy, the address to that pointer is used which
will lead to copying undefined data. Fix the pointer/address used in
memcpy.

BUG=None
BRANCH=dedede
TEST=Build Kracko, Drawcia and Metaknight mainboards which use this
function.

Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Found-by: Coverity CID 1458053, 1458054.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:50:24 +00:00
Raul E Rangel 4693f3dfe9 timestamp,vc/google/chromeos/cr50: Add timestamp for enable update
cr50_enable_update takes a non-trivial amount of time.

TEST=Boot guybrush and dump timestamps
 553:started TPM enable update                         3,615,156 (444)
 554:finished TPM enable update                        3,632,810 (17,654)

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I522d0638a4a6ae9624965e49b47bca8743c3206c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05 10:50:06 +00:00
Paul Menzel 2efcafa7b0 device/resource_allocator_v4: Only highlight log message with ===
Currently, four instead of three = are used in one log message.

    Done reading resources.
    ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
    === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===

As the ending mark is `===` change it to `===` in the beginning.

    Done reading resources.
    === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
    === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===

Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56045
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:49:53 +00:00
Arthur Heymans 028b94b765 sb/intel/i82801gx: Prepare for x86_64
Do the usual int conversions.

TESTED: BUILD_TIMELESS=1 produces identical image on foxconn/g41m.

Change-Id: Idebfe4669854b307bee653df6d93e46ae3f39dec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56020
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:49:12 +00:00
Arthur Heymans 4d06ff0faa nb/intel/x4x: Use write32p and read32p
This removes the need for type conversions all over the place.

Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:48:41 +00:00
Arthur Heymans 2aeb2a1561 nb/intel/x4x: Prepare for x86_64 support
Do the usual type conversions

TESTED: Same image with BUILD_TIMELESS=1

Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:48:27 +00:00
Arthur Heymans bc7b63fa6b cpu/intel/car/p4-netburst: Prepare for x86_64
Use proper car symbols.

Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:48:15 +00:00
V Sowmya 3476410039 mb/intel/adlrvp: Update the FIVR configurations
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-05 10:47:31 +00:00
V Sowmya 418d37e689 soc/intel/alderlake: Add support to update the FIVR configs
This patch adds the supports to update the optimal FIVR
configurations for external voltage rails via devicetree.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05 10:47:17 +00:00
Tim Wawrzynczak 912a2353d2 mb/google/brya/brya0: Enable Crashlog
brya0 is a reference and development platform, therefore it would be
helpful to have Crashlog enabled.

Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-05 10:46:56 +00:00
Tim Wawrzynczak 56adcc8fb7 mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
The brya EC supports S0ix hang detection, but it was not enabled in
coreboot as well, masking that event out of S0ix, therefore add it in to
the EC S0ix wake mask.

TEST=After EC prints "Warning: Detected sleep hang! Waking host up!",
the host actually wakes up

Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-05 10:46:48 +00:00
Dtrain Hsu f294378622 mb/google/dedede/var/cret: Disable SDCard controller
Cret doesn't support SDCard. Disable SDCard contorller for Cret.

BUG=b:191232222
TEST=Build and boot to check lspci

Cq-Depend: chromium:2993724
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-05 10:46:22 +00:00
Varshit B Pandya f09b39bf88 soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
Correct Bus and Device for THC0 and THC1

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-05 05:27:26 +00:00
Alexander Couzens ca4e6aa3ad supermicro/x11: enable COMB via LPC
Allow to use the 2nd COM port of the AST2400 which can be also used via
IPMI/serial-over-lan.

Change-Id: I6f9c85b1f5428d3c3acf7a2f20296134c4611b1e
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-04 13:11:55 +00:00
Raul E Rangel db28040ee1 util/cbfstool: Allow setting alignment for payload
The -a flag was already implemented, it just wasn't exposed for the
add-payload command.

Setting the alignment of the payload will enable using the SPI DMA
controller to read the payload on AMD devices.

BUG=b:179699789
TEST=cbfstool foo.bin add-payload -a 64 ...

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02 23:14:33 +00:00
Raul E Rangel f702705c04 soc/amd/common/espi: Fix debug message log level
BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02 23:13:03 +00:00
Raul E Rangel 43e993b3b0 drivers/intel/fsp2: Change FSPS returned message to INFO
This message is not an error, but just informational.

BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02 23:12:54 +00:00
Raul E Rangel 35e27b34f5 soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.

BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.
Also boot Ezkinil and verify microcode was also updated.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02 23:12:34 +00:00