Commit Graph

42928 Commits

Author SHA1 Message Date
Arthur Heymans 8585eabc5d util/abuild: Fix overriding results with the default configuration
I a file in configs/* has no suffix, then the default configuration
will override the results of the build generated by the configfile
from configs/*. Fix this by adding a '_' to the buildname.

Change-Id: Ic47105fafca41f1905a6569943079623bec5405a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-13 20:20:15 +00:00
Felix Singer 4dcac13043 intel/kblrvp: Move lockdown config to baseboard devicetree
Clean up lockdown configuration and move it to the baseboard's
devicetree.

Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it
for the rvp8 variant for consistency as well.

Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains
identical. intel/rvp8 changes, as expected.

Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13 18:47:00 +00:00
Felix Singer 1be296c1e7 mb/intel/kblrvp/variants: Fix indentation and remove empty lines
Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56211
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13 18:46:44 +00:00
Ronak Kanabar 16da569df9 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00
The headers added are generated as per FSP v2237_00.
Previous FSP version was v2207_01.
Changes Include:
- Add VccInAuxImonIccImax in FspsUpd.h
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h

BUG=b:192199787
BRANCH=None
TEST=Build and boot brya

Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c
Cq-Depend:chrome-internal:3970327,chrome-internal:3925290
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13 15:14:56 +00:00
Meera Ravindranath 91a1276d53 soc/intel/alderlake: Implement WA for DDR5 DIMM modules
The coreboot SMBus driver requires additional changes to accomodate
the DDR5 EEPROM read which has resulted in a broken code flow for boot.

This CL serves as a temp WA to let FSP perform the SPD read for DDR5
and pass SPD addresses to FSP UPD array.

BUG=b:180458099
TEST=Build and boot DDR5 adlrvp to OS

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13 14:30:07 +00:00
Tim Wawrzynczak 82225b81f8 soc/intel/alderlake: Add (and fix) devices in IRQ table
Some devices were missing from the IRQ table, and this lack of
IRQ programming for the devices (although unused), was causing S0ix
entry to fail.

BUG=b:176858827
TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle
correctly upon entry/exit from S0ix

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-13 14:29:33 +00:00
Felix Singer 989c7c4f8b mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown.

Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13 12:42:57 +00:00
Ryan Chuang f1cf5ee893 vc/mediatek/mt8195: Remove redundant code
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-13 01:46:30 +00:00
Felix Held 7cf3787a53 security/intel/txt: use mca_get_bank_count()
Use the common mca_get_bank_count function instead of open-coding the
functionality to get the MCA bank number.

Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12 21:48:37 +00:00
Felix Held 46e6a5883e Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"
This reverts commit ce0e2a0140 which was
originally introduced as a workaround for the bug that the Linux kernel
doesn't know what to do with type 16 memory region in the e820 table
where CBMEM resides and disallowed accessing it. After depthcharge was
patched to mark the type 16 region as a normal reserved region, the
Linux kernel now can access the BERT region and print BERT errors. When
SeaBIOS was used as payload it already marked the memory region
correctly, so it already worked in that case.

After commit 8c3a8df102 that removed the
usage of the BERT memory region reserved by the FSP driver by the AMD
Picasso and Cezanne SoCs and made them use CBMEM for the BERT region,
no other SoC code uses this functionality. The Intel Alderlake and
Tigerlake SoCs put the BERT region in CBMEM and never used this reserved
memory region and the change for the Intel server CPU to use this was
abandoned and never landed in upstream coreboot. AMD Stoneyridge is the
only other SoC/chipset that selects ACPI_BERT, but since it doesn't
select or use the FSP driver, it also won't be affected by this change.

TEST=Behavior of the BERT code doesn't change on Mandolin

Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 17:34:00 +00:00
Felix Held ced76f732f include/cpu/x86/msr: fix MCG_CTL_P definition
MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of
that MSR contain the number of MCA banks being present on the CPU. At
the moment this definition of MCG_CTL_P is unused.

Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12 15:45:06 +00:00
Felix Held 7b6a397eec security/intel/txt: add missing cpu/x86/msr.h include
msr_t and a few other things used in here are defined in cpu/x86/msr.h,
so include it directly in this file.

Change-Id: I7a3299381ff54b7665620861dec60642f27bac8d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12 15:29:29 +00:00
Felix Held 4add9923c0 soc/amd/*/mca: use mca_get_bank_count()
Use the common mca_get_bank_count function instead of open-coding the
functionality to get the MCA bank number. Also re-type the num_banks
variable from signed in to unsigned int, since the number of MCA bank is
always positive.

Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12 15:29:13 +00:00
Varshit B Pandya f48eecbbe0 mb/google/brya: Update generic device number for mipi_camera device
If two generic devices use the same number, device coming later
overrides the earlier device, as a result of this the static.c has
only one device.

In the case where we have UFC set to UFC_USB, this will result in
no IPU device scope in SSDT, since its entry will be set to disbled
after UFC probe.

TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 15:16:40 +00:00
Felix Held 2828fee7e0 cpu/amd/*/model_*_init: use mca_get_bank_count()
Use the common mca_get_bank_count function instead of open-coding the
functionality to get the MCA bank number. Also re-type the num_banks
variable from signed in to unsigned int, since the number of MCA bank is
always positive.

Change-Id: I70ad423aab484cf4ec8f51b43624cd434647aad4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12 13:33:03 +00:00
Felix Held 3f1b70640a include/cpu/x86/msr: add mca_get_bank_count function
In multiple locations within the coreboot tree the IA32_MCG_CAP MSR gets
read and masked with MCA_BANKS_MASK to get the number of available MCA
banks on the CPU, so add this to the common code to avoid duplication
of code.

Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-12 13:32:46 +00:00
Raul E Rangel 3acc515bef soc/amd/{cezanne,common}: Enable IOMMU PCIe Device
This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.

BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12 12:30:33 +00:00
Tim Wawrzynczak c4ca2f6396 acpi: Add function to simplify If (CondRefOf (..)) sequences
The new function is called acpigen_write_if_cond_refof(), and it must
be paired with a following acpigen_write_if_end() call.

Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-12 07:34:44 +00:00
Paul Menzel f16a5ec871 vc/amd/sb800: Cast to UINT32 for shift out of bounds fix
It’s defined as `unsigned char`.

    SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:643:53
    ubsan: unrecoverable error.

Found-by: UBSAN
Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12 07:32:24 +00:00
Paul Menzel 4715c6219c vc/amd/sb800: Cast variable to 32-bit before shift
SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/Gpp.c:151:61
    ubsan: unrecoverable error.

Found-by: UBSAN
Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12 07:32:08 +00:00
Paul Menzel 69569e5306 vc/amd/sb800: SBCMN: Cast to 32-bit before shift
SB800: sb_Before_Pci_Init
    shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57
    ubsan: unrecoverable error.

Found-by: UBSAN
Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 07:31:52 +00:00
Maulik V Vaghela 9c7122f1e8 drivers/intel/usb4/retimer: remove redundant structure member group(PLD)
Currently, we get PLD information from USB port structure itself, so
devicetree does not need to fill PLD structure anymore. Thus remove
obsolete variable.

Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:48 +00:00
Maulik V Vaghela 91c38c8c8d mb/google/brya,primus,voxel: Update controller field for tbt_dma entries
We need to reference correct USB port number for driver to
identify type-C port number correctly.

BUG=b:189476816
BRANCH=None
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.

Change-Id: I20c088ee81610155067abad086eba8d72f73ad60
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:39 +00:00
Maulik V Vaghela 0f7e086229 drivers/intel/usb4/retimer: Update code to assign correct port number
Since TBT controller can have maximum 2 ports per controller, our
code will loop over DFP structure twice and determine port number.

Retimer driver used to assign port number as below:
1. Check if power GPIO is assigned for particular DFP entry or not
2. If entry is there, assign loop count as port number

Since loop count is 2, retimer will never assign port number = 2
even if it's present. In case of more than 1 controller, port number
assigned will still be 0 or 1 even though actual port index might
be 2 or 3. This will create an issue where even if you do transaction
on device on controller 2 (port index 2 or 3), EC will route it on
port 0 or 1 due to incorrect port index.

Update the driver flow as per below to handle this scenario:
1. Check if power GPIO is assigned for particular DFP entry or not
2. Get USB port number from config since it's stored in usb port
   information under devicetree
3. Pass the port number to ACPI SSDT and EC code

Above changes will ensure that we're assigning correct port
number as per calculation and EC will use correct port index.

BUG=b:189476816
BRANCH=None
TEST=Checked that retimer firmware update works on both ports and update
happens on correct port index.

Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:32 +00:00
Maulik V Vaghela 8e885a57b1 drivers/usb/acpi: Create function to get PLD information
Create a separate function to get PLD information from USB device.
This is helpful in retimer driver where we can attach same USB
port information to retimer instance and we can avoid duplication
of information.

BUG=None
BRANCH=None
TEST=Check if code compiles and function returns correct value

Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 07:29:24 +00:00
Sunway 43b2212d13 mb/google/kukui: Add a new config 'Munna'
Introduce a new board 'Munna' to Kukui family.

BUG=None
TEST=make # select Munna
BRANCH=kukui

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56169
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 07:29:10 +00:00
Subrata Banik bf7505519c soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

Test=Boot ADLRVP and check cbmem -c | grep 'CBFS: Found'
lists all stages.

Change-Id: I38fd74c2edd71ce9f6c08db9dacb18e553745877
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-12 04:37:07 +00:00
Raul E Rangel ae47803721 soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared
The Majolica UEFI ACPI tables have this listed as shared. It's already a
level interrupt, so no reason it shouldn't be shared.

This change makes it so Windows can correctly initialize the GPIO
controller.

BUG=b:186212501
TEST=Boot guybrush to windows and see GPIO controller functional. Also
boot guybrush to windows and verify GPIO controller still works.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12 04:35:07 +00:00
Tim Wawrzynczak 251d40596c soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()
Previously, irq_program_non_pch() was only programming the IRQ line, but
the pin is required as well.

BUG=b:176858827

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56174
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 04:34:14 +00:00
Tim Wawrzynczak 9d4fda8579 soc/intel/alderlake: Add missing devices to pci_devs.h
There were some devices missing from pci_devs.h:
1) GNA
2) I2C6 and I2C7
3) UART3, UART4, UART5, UART6
4) UFS
5) GSPI4, GSPI5, GSPI6

BUG=b:176858827

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 04:33:09 +00:00
Felix Held e9e031672c soc/amd/picasso,stoneyridge/mca: remove unneeded line break
Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56180
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 04:30:39 +00:00
Kangheui Won 3d439ffeef mb/google/guybrush: enable psp_verstage by default
Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default.

BUG=b:182477057
TEST=boot guybrush

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12 04:29:56 +00:00
Casper Chang f8ece9113a mb/google/brya/variants/primus: Update GPIO for PS8811 init
Route GPP_D14 to USB_A1_RT_RST_ODL for PS8811 init sequence

BUG=b:193099675

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 04:29:22 +00:00
V Sowmya af42906efa soc/intel/alderlake: Set max Pkg C-states to Auto
This patch configures max Pkg C-state to Auto which limits the max
C-state to deep C-state

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12 04:28:39 +00:00
Thejaswani Putta 250356c0c1 mb/intel/adlrvp_m: Enable EC software sync
This patch enables CONFIG_VBOOT_EARLY_EC_SYNC.
EC software sync will be performed in romstage.

BUG=None
BRANCH=None
TEST=Verify EC software sync works on adlrvp_m

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 04:24:43 +00:00
David Wu 07375cb384 mb/google/brya: Create kano variant
Create the kano variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:193052432
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KANO

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 04:13:01 +00:00
James Lo 543b32f60d soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability
Update IO driving setting for pmif spi.

Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 02:54:36 +00:00
Ryan Chuang e46cd138ff vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
Add the implementation for vcore voltage control.
Also remove the reporting of vio18 because it is fixed during DRAM init,
and we won't provide drivers for reading or writing it.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 02:54:23 +00:00
Rex-BC Chen 2555bd410b vc/mediatek/mt8195: add FOR_COREBOOT define
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12 02:54:01 +00:00
Tim Wawrzynczak 6db9dccc57 soc/intel: Fix microcode loading
Commit 1aa60a95bd broke microcode loading for chipsets that have a
microcode blob with a total_size field set to 0. This appears to be
support for older chipsets, where the size was set to 0 and assumed to
be 2048 bytes. The fix is to change the result of the subtraction to a
signed type, and ensure the following comparison is done without
promoting the signed type to an unsigned one.

Resolves: https://ticket.coreboot.org/issues/313
Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56153
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-09 11:49:02 +00:00
Krystian Hebel 84a156c77e ppc64/byteorder.h: define use of big endian
All of the build configuration is set to produce big endian image on PPC64.
In addition, the toolchain produced by coreboot-sdk does not include little
endian libraries so it is not possible to build LE image even when that
configuration is changed.

This patch changes byte order definition which is required for proper work
of functions that deal with endianness, like read_{le,be}*() or
{le,be}*toh().

It also revealed bugs related to the endianness on BE targets that are
addressed in the following patches.

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Id31328a832d11db20822733304b0ae477e858d25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-09 11:46:30 +00:00
Julius Werner 4676279151 Revert "Makefile.inc: Drop the cbfs master header from non-X86"
This reverts commit d109354c0f.

Reason for revert: Breaks libpayload CBFS code when accessing
non-default CBFS.

BUG=b:193093750

Change-Id: Id7f47406e6126f19e1fd6bc9d33c8c9d0cb9450d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-09 00:52:10 +00:00
Zheng Bao ec5a5d7abf amdfwtool: Fix the NULL pointer in parameters
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 18:52:00 +00:00
Zheng Bao 0fc87e31e0 amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-08 16:04:09 +00:00
David Wu 595b940ef0 mb/google/volteer/var/voema: Remove stop delay time for ELAN TS
Remove register "generic.stop_delay_ms" and measure data, it still
can meet elan touchscreen specification that reset pull high to
I2C time > 150ms (T3 > 150ms).

BUG=b:185308246
TEST=Measure the T3 delay time is greater than 150ms on voema

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 15:53:39 +00:00
Wisley Chen 440893df3c mb/google/brya/var/redrix: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

MT53E1G32D2NP-046 WT:A
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
MT53E512M32D2NP-046 WT:E
H9HCNNNCPMMLXR-NEE
K4UBE3D4AA-MGCR
H9HCNNNFAMMLXR-NEE
MT53E2G32D4NQ-046 WT:A

BUG=b:190818098, b:190874372, b:192052098
TEST=build

Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55885
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08 15:52:37 +00:00
Wisley Chen 61cef57e62 mb/google/brya: Create redrix variant
Create the redrix variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:192052098
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_REDRIX

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-08 15:51:45 +00:00
V Sowmya d5ab163086 mb/google/brya0: Update the FIVR configurations
This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:50:57 +00:00
Sumeet Pawnikar 590eb2bb9c Documentation/drivers/dptf: Add oem variables support
Add oem variables information with usage example.

BRANCH=None
BUG=b:187253038
TEST=Built and tested on dedede board

Change-Id: I45db17f6ee3328da28f985c6854d65a430c9c61b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:49:55 +00:00
Sumeet Pawnikar 681a59d5c3 mb/intel/tglrvp: Update Power Limit2 minimum value
Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.

BUG=None
BRANCH=None
TEST=Build and test on tglrvp system

Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08 15:48:47 +00:00