Commit Graph

42928 Commits

Author SHA1 Message Date
Ronak Kanabar 89316b6c6f soc/intel/jasperlake: Select DISPLAY_FSP_VERSION_INFO_2
Select DISPLAY_FSP_VERSION_INFO_2 for Jasper Lake soc.

BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.

Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1

Change-Id: If68b704c4304357b0046a510545fc213d7ed5887
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45907
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-26 10:06:40 +00:00
Arthur Heymans 5cb24d4522 soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard
It looks like the 'clear_car' code does not properly fill the required
cachelines so add code to fill cachelines explicitly.

Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26 10:06:23 +00:00
Johnny Lin e273a02d25 util/ifdtool: Add Xeon SP Lewisburg PCH platform support under IFDv2
After commit 8c082e5fe (util/ifdtool: Use -p platform name
to detect IFDv2 platform and chipset) w/o this xeon_sp/cpx would be
detected as IFDv1 and see build error.

Fixes: 8c082e5fe ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I444e7d35a85d9d42fc25d654e57386f38cf1ec85
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26 10:05:53 +00:00
Casper Chang 181fce25d9 mb/google/brya/variants/primus: init overridetree for Primus
init overridetree.cb based on the schematic ver MB_20210616C.

BUG=b:191897776, b:191897775

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I185b36e34d24b703092e3798e91c70ce3912b11f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-26 04:07:49 +00:00
Frans Hendriks 57e55148f4 mb/facebook/fbg1701/fbg1701/vboot-rw.fmd: Correct FMD statement
CB:55452 uses FMAP instead of "cbfs master header".
The flash size statement in vboot-rw.fmd does not contain the start
address, resulting in a non-booting system.

Add start address to FLASH statement.

BUG = N/A
TEST = Boot Facebook FBG1701

Change-Id: Id05ad33babb416a37c657b25cdb1e98d47c1a56d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-25 15:53:10 +00:00
Matt DeVillier 8f9ee36c53 mb/google/{octopus,reef}: Fix size of SI_BIOS region in default.fmd
0xf7f000 - 0x1000 = 0xf7e000, not 0xf6f000.

This fixes build failure when selecting the option to validate the
layout using the flash descriptor (CONFIG_VALIDATE_INTEL_DESCRIPTOR)

Test: build google/casta successfully with IFD validation selected

Change-Id: I6df67f76f5d766a9f4f85ffc3e1f0de4a241f509
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55815
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 15:52:51 +00:00
Arthur Heymans e243a60efe security/intel/cbnt: Remove fixed size requirement
The CBnT provisioning tooling in intel-sec-tools are now cbfs aware
and don't need to have a fixed size at buildtime.

Tested on OCP/Deltalake with CBnT enabled.

Change-Id: I446b5045fe65f51c5fa011895cd56dbd25b6ccc7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55821
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 15:52:05 +00:00
Martin Roth 8a85a84fac Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80s
Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in
bootblock.

BUG=b:191370340
TEST: Build with & without the option enabled

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-25 15:51:20 +00:00
Malik_Hsu b8bba6519e mb/google/brya/variants/primus: add dram part id
This change adds mem_parts_uesd.txt that contains the only
memory parts used by primus for Proto build and Makefile.inc
generated by gen_part_id.go using mem_parts_used.txt.

BUG=b:186091208,b:189169995

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I423fd9ad4349c51c6e6b166734ae706509d6ac3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25 15:03:14 +00:00
Sheng-Liang Pan 36572cade4 mb/google/volteer/var/chronicler: add chronicler memory configuration and gpio and devicetree settings
add memory configuration for chronicler,
based on schematic and gpio table, update gpio and devicetree settings for chronicler.

BUG=b:187318819
BRANCH=None
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
verify bootable with chronicler

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Id5524b97a236dcc64d18ab1cd2ce13f6bb2d998f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55340
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 06:30:44 +00:00
Angel Pons adeac8d4f7 soc/intel/apollolake: Drop `xdci_can_enable()` call
The `xdci_can_enable()` function is called earlier to configure FSP-S
UPDs. If it returned false, then the xDCI device will be disabled and
the second `xdci_can_enable()` call will never be evaluated.

Change-Id: I4bd08e3194ffccc79c8feaf8f34b2bb4077f760a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55789
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 06:28:11 +00:00
V Sowmya 6464c2aa4f soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param
This patch fixes the typo introduced in commit b03cadf for renaming
FSP_S_CONFIG param name to s_cfg.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I0a9b500e528c68033008f3f8955d6c9c9ba8a737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-25 06:26:46 +00:00
Nico Huber f22f408956 cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.

This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.

Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-25 04:28:36 +00:00
Frans Hendriks cd85aac434 mb/facebook/fbg1701/fbg1701/Kconfig: Update VBOOT key location
Error Could not add [key.vbpubk]: too big occurs, when Eltan verified boot is enabled.

Update value of VENDORCODE_ELTAN_VBOOT_KEY_LOCATION.

BUG = N/A
TEST = Boot Facebook FBG1701 with Eltan verified boot enabled.

Change-Id: I1faecd189915985df633ac74627fd872ce8867f0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25 04:25:42 +00:00
Angel Pons 50b92f9a82 soc/intel/apollolake/xdci.c: Use `dev` parameter
The `dev` parameter already points to the xDCI device.

Change-Id: I122cc642c86b30804dd1176f77f4e2e1ebea4aa0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55788
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:24:09 +00:00
Angel Pons 9bf9adae13 soc/intel/skylake: Use `devfn_disable()` to handle XDCI
Done for consistency with other Intel SoCs. This allows moving the
pattern inside a helper function.

Change-Id: If95c4b6c1602e56436150a931210692f14630694
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55787
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:22:42 +00:00
Angel Pons 7ff3f31cd1 soc/intel/skylake: Use `is_devfn_enabled()`
Use the `is_devfn_enabled()` function for the sake of brevity.

Change-Id: Ic848767799e165200f26c2d5a58fbd3b72b9c240
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55786
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:21:56 +00:00
Kevin Chiu bb0c404e6e mb/google/octopus: add audio codec into SSFC support for Garg/Garfour
BUG=b:191213716
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I2d5738442d2c173fd5b4802d8b5dff76b428c6f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55564
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:20:11 +00:00
Ronak Kanabar f7e8adac7b edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h
Update MdePkg/Include/IndustryStandard/SmBios.h to avoid compilation
errors through safeguarding definitions with DISPLAY_FSP_VERSION_INFO_2
Kconfig.

BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patches in relation chain
and verify the version output prints no junk data observed.
Couple of lines from logs are as below.

Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1

Change-Id: I9698861be1f969ddca7f171767a54ac486502c74
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45906
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:19:08 +00:00
Tim Wawrzynczak 064ca18463 soc/intel/common/cse: Add support for sending CSE End-of-Post message
The CSE expects the boot firmware to send it an End-of-Post message
before loading the OS. This is a security feature, and is done to ensure
that the CSE will no longer perform certain sensitive commands that are
not intended to be exposed to the OS.

If processing the EOP message fails in any way on a ChromeOS build, (and
not already in recovery mode), recovery mode will be triggered,
otherwise the CSME BWG will be followed, which is in the following
commit.

BUG=b:191362590

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f667905f759cc2337daca4cc6e09694e68ab7e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-25 04:17:23 +00:00
Yu-Hsuan Hsu 45c46b6c39 mb/google/guybrush: Change ACPI HID for machine driver
To avoid from using same the name AMDI5682 as Zork, changing to use
AMDI1019. The corresponding kernel change is on CL:2929864

BUG=b:189297564
TEST=Audio works with the corresponding kernel change.

Cq-Depend: chromium:2929864
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:15:30 +00:00
Bernardo Perez Priego b4a09c03f7 soc/intel/alderlake: Update s0ix cstate table
Cstate C7 is not supported in ADL, replacing this unsupported state
with C6 in the s0ix cstate table.

BUG=None
TEST=Boot device to OS.
     Print supported CStates and latencies.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:10:26 +00:00
Alice Sell b5a8586fe4 mb/asus/p5q_se: Add initial support
This motherboard is almost identical to the ASUS P5QL PRO,
with the only noticeable difference being that the ASUS P5Q SE
has a P45 MCH while the P5QL PRO has a P43 MCH. Few changes were
required.

Signed-off-by: Hunter Sell <alicelyralain@gmail.com>
Change-Id: I36612bac16a79f05f3fe57e535e4ba3c73790a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25 04:09:05 +00:00
Angel Pons 9d5c94ac7a cpu/qemu-x86/Kconfig: Drop redundant selects
The `ARCH_POSTCAR_X86_32` and `ARCH_POSTCAR_X86_64` options are already
selected indirectly. There's no need to explicitly select them.

Change-Id: Iaa2e99e6f0765741fc5af67180d116bb6cc23d38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55757
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 04:07:21 +00:00
Mark Hsieh 72bdda2582 mb/google/brya: add generic LPDDR4 SPDs for Gimble
Add Makefile.inc to include three generic LPDDR4 SPDs for the following
parts for Gimble:

  DRAM Part Name                 DRAM ID to assign
  MT53E512M32D2NP-046 WT:E       0 (0000)
  H9HCNNNCPMMLXR-NEE             1 (0001)
  H9HCNNNBKMMLXR-NEE             0 (0000)

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I60f95ac5ed7f3134882f6580335ec33632676796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-06-25 03:14:55 +00:00
Mark Hsieh 62b9ed27ea mb/google/brya/variants/gimble: set up gpio
Set the GPIO configuration of gimble

BUG=b:191213263

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I667943578a2bf58cc5841564b8df5b6469d7594b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55717
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-25 03:14:32 +00:00
Zanxi Chen 4dce0990f9 mb/google/trogdor: Add new vaviant mrbland
New boards introduced to trogdor family.

BUG=b:191800434
BRANCH=none
TEST=make

Change-Id: I93b74e79188bd0cc36c8b48e552230ae0d6f593a
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-24 21:06:20 +00:00
Arthur Heymans 890d4fbea6 arch/x86/bootblock.ld: Align the bottom of the bootblock to 64 bytes
Align the bootblock size to 64 bytes because:
- cachelines are often 64 bytes large
- Bootguard/CBnT requires a 64 byte alignment

Change-Id: I69cdacdd15bfca1b91b6f271f2ff76889969fd91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-06-24 11:22:54 +00:00
Arthur Heymans 6da7fa26b0 soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKE
Intel Apollolake does not support the bootguard MSRs 0x139 MSR_BC_PBEC
and 0x13A MSR_BOOT_GUARD_SACM_INFO.

Change-Id: Ief40028a1c85084e012a83db8080d478e407487b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-24 10:02:06 +00:00
Arthur Heymans cd96fed5dc soc/intel/cache_as_ram.S: Add macro to detect bootguard nem
Change-Id: I3867fce29d23b647fad9845b9a5c08bb949fa354
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 09:00:50 +00:00
Subrata Banik 0007fa96a1 soc/intel/alderlake: Update mainboard_memory_init_params() argument
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.

Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:55:12 +00:00
Subrata Banik b03cadf84b soc/intel/alderlake: Refactor soc_silicon_init_params function
This patch create separate helper functions to fill-in required
FSP-S UPDs as per IP initialization categories.

This would help to increase the code readability and in future
meaningful addition of FSP-S UPDs is possible rather adding UPDs randomly.

TEST=FSP-S UPD dump shows no change without and with this code change.

Change-Id: Iba51aebc74456449e24e51e2f309f14f951464a0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 07:54:46 +00:00
Subrata Banik c0983c9e9b soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg
Align FSP-S UPD structure (FSP_S_CONFIG) variable name (s_cfg) as FSP-M
UPD structure variable (m_cfg).

TEST=Able to build and boot ADLRVP to ChromeOS. FSP-S UPD dump shows
no change in UPD values with this CL.

Change-Id: I795f733f5f0cc64d3a556a1cd401323b35ba5a23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:54:23 +00:00
Subrata Banik 6f1cb40ee6 soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function
Align platform_fsp_silicon_init_params_cb() function implementation
with romstage/fsp_params.c file platform_fsp_memory_init_params_cb() as:
|- Override FSP-S Arch UPD(s) using arch_silicon_init_params().
|- Override FSP-S SoC UPDs using soc_silicon_init_params().
|- Override FSP-S Mainboard UPDs using mainboard_silicon_init_params().

TEST=FSP-S UPD dump shows no change without and with this code change.

Change-Id: I4cf0b8423fb4038a7feddd97ff585027b3012605
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24 07:53:47 +00:00
Kangheui Won a8b419b37b mb/google/guybrush: configure eSPI mux on psp_verstage
Temporarily set eSPI mux in verstage_mainboard_early_init.
Ideally cezanne code should have common function to do this and
mb-specific code would just call it, but for now PCI access doesn't work
in the PSP so we can't do it.

AMD team confirmed that the current PSP doesn't configure LPC so we
don't have to disable LPC when configuring eSPI mux so we can
temporarliy skip the LPC part here.

BUG=b:183149183
TEST=boot guybrush with psp_verstage

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I8317409fa5efd1adffc184d75affbb4d305183f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-24 04:16:47 +00:00
Ryan Chuang 2ecb0ed266 vc/mediatek/mt8195: Allow adjusting DRAM voltage in DRAM calibration
To support DRAM HQA HV/LV test, add an interface for adjusting the DRAM
voltage in DRAM fast calibration flow.
Normal boot flow will not be affected.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I4dbb4cb546e6e60693743ffe26b0df28ea501618
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55752
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 03:15:21 +00:00
Rex-BC Chen 506b4c9093 mb/google/cherry: Implement regulator interface
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iab58edd019ccf9130e96fae55f147ab20cd0f45b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55751
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24 03:15:00 +00:00
Ryan Chuang da63f09b80 mb/google/cherry: Initialize DPM in romstage
Add initialization of DPM drvier used by DRAM calibration test.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I8bd10864267dfa4db8528d40483eccee2d05c1d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24 03:14:28 +00:00
Ryan Chuang d5b0000856 mb/google/cherry: Add mt6360 driver for PMIC access
Add initialization of mt6360 drvier used by DRAM calibration test.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Id74835d8395afac9e7e2c987a0a033f1b524fbfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24 03:14:05 +00:00
Ryan Chuang a9be096fa7 soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flow
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If2e9d8a4dcfad28c48a2b5fa7c92f70fae879e67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-24 03:13:53 +00:00
Karthikeyan Ramasubramanian 6ce71e3bb1 mb/google/guybrush: Indicate the presence of ACP DMIC
In order to enable ACP DMIC hardware runtime detection, indicate that
ACP DMIC is present.

BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated in the ACP device.

Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 19:19:33 +00:00
Karthikeyan Ramasubramanian 4ce48b3a37 soc/amd/common/acp: Populate _WOV ACPI method
In order to support Audio Co-processor (ACP) DMIC hardware runtime
detection on the platform, ACPI _WOV method is populated on the
concerned ACP device. This method returns the ACPI Integer value as 1
if ACP DMIC exists on the platform.

BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated under the scope of ACP device.
    Scope (\_SB.PCI0.GP41.ACPD)
    {
        Method (_WOV, 0, NotSerialized)
        {
            Return (One)
        }
    }

Change-Id: Ide84f45f5ea2ae42d5efe71ac6d1595886157045
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55029
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 19:19:19 +00:00
Martin Roth 6662fe60e1 soc/amd/cezanne: Init eSPI early if required
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure
eSPI as early as possible in the x86 boot sequence.

We found that there are situations that can cause the system to hang if
there are any port80h postcodes sent out before eSPI is initialized.

BUG=b:191370340
TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 19:01:16 +00:00
Martin Roth 7c21c20821 mb/google/guybrush: Add guybrush specific AMDFW config file
This takes the "generic" AMD firmware config file from the cezanne
directory and removes pieces unnecessary for guybrush.

Removed:
- PSPTRUSTLETS_FILE         TypeId0x0C_FtpmDrv_CZN.csbin
- PSP_MP2FW0_FILE           TypeId0x25_Mp2Fw_CZN.sbin
- PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
- DRTMTA_FILE               TypeId0x47_DrtmTA_CZN.sbin
- PSP_MP2CFG_FILE           MP2FWConfig.sbin

BUG=b:187103438
TEST=Build & Boot

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5a0ed1edd7616a890f906b7f3e4a7d364758ca47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23 19:00:17 +00:00
David Wu 7abdb6560a mb/google/dedede/var/magolor: Enable weida touchscreen for magister
Add weida touchscreen support for magister.

BUG=b:191633024
BRANCH=dedede
TEST=Build and verify that touchscreen works on magister.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3de6a84d2d58ef87f0ae13e8a117a980a0210ac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Randy Lai <randy.lai@weida.corp-partner.google.com>
2021-06-23 18:26:14 +00:00
Felix Held 8c3a8df102 soc/amd/common/block/cpu/noncar/memmap: move BERT region back into CBMEM
The original reason the BERT table was moved out of CBMEM was because
the OS was not able to access the region. This happened because the
CBMEM region was marked as type 16 in the e820 table. The OS isn't aware
of this type, so it prevents any drivers from accessing it. Depthcharge
now correctly labels the CBMEM region as reserved in the e820 table so
we can move the BERT table into CBMEM.

TEST=BERT ACPI table generation still works on AMD/Mandolin with SeaBIOS
as payload and BERT region inside CBMEM is inside a BIOS-e820 reserved
range. BERT generation also works on Zork with depthcharge.

Link: https://crrev.com/c/2939677
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie640e91c19ae5f9b275cc333284b4be34211fbf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-23 14:36:19 +00:00
Zhi Li 3694cc737a mb/google/dedede/var/sasukette: Change ELAN touchpad driver
Use drivers/i2c/hid can't update firmware by kernel update script,
so change to drivers/i2c/generic.

BUG=b:188602529
BRANCH=dedede
TEST=can update ELAN touchpad firmware(277.0_1.0) by kernel script

Change-Id: I3592403fe5d0f8d0f67059f8296277e3c028c117
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55248
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 14:35:39 +00:00
Arthur Heymans ab090a11ee mb/{fb/fbg1701,portwell/m107}: Don't select HAVE_FSP_BIN
This selected by default if 3rdparty/fsp is used. There is no need to
override this behavior in the mainboard Kconfig.

Change-Id: I01ee2e90e0eceaa3100d911b5460cf99f413b185
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-06-23 14:35:27 +00:00
Frans Hendriks 6cd4cfa30d mb/facebook/fbg1701/Kconfig: Correct dependency
Config items depends on USE_VENDORCODE_ELTAN but are VBOOT specific.

Correct dependency of these items on VENDORCODE_ELTAN_VBOOT.

BUG = NA
TEST = Boot facebook FBG-1701 with possible combinations of Eltan
security.

Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: Icd1c3e5c70ca562190308752f45aac734826649a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52132
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 14:35:08 +00:00
Kyösti Mälkki 6c7e945ab2 soc/intel/common: Fix X2APIC NMI entry in ACPI MADT
For X2APIC mode, replicate the APIC NMI entry flags and
intention to address all the logical processors.

Change-Id: I9c0537a3efba942329f80d7cfdbd910b8958516f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55182
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 10:14:17 +00:00