ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: I9f55cc033b5672917520b139444bc614462c4a05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SOC DRAM team suggested to delay at least 1us after setting new
voltage in PMIC wrapper so the new value can be effective.
BRANCH=kukui
BUG=b:142358843
TEST=emerge-kukui coreboot
Change-Id: I19d236769c3c0c87513ea4a0a3f64b83e3a844c2
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36254
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add VPD variables for enabling/disabling FRB2 watchdog timer and
setting the timer countdown value. By default it would start the
timer and trigger hard reset when it's expired. The timer is
expected to be stopped later by payload or OS.
Right now the timer is started after FSP-M. Ideally it should be
before FSP-M (to detect memory training error).
Tested on OCP Mono Lake.
Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a function for initializing and starting FRB2 timer with the
provided countdown and action values, and a stop function for
stopping the timer.
Tested on OCP Monolake.
Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
As fmaptool can now handle the offset computation for every mentioned
region in the fmap file on its own there is no need to provide the
offset in the fmd file anymore. This patch clears this out so that the
files are way more readable now.
Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
RT1011 is a smart amplifier. It needs to know speaker related parameters
including speaker resistor value and temperature when the calibration is
done in order to run Dynamic Speaker Management (DSM) algorithm on chip.
The purpose of DSM is to protect speaker when the volume is large.
The calibration data of speaker is stored in VPD in factory.
This driver is needed to read data from VPD and write to ACPI _DSD when
config CHROMEOS_DSM_CALIB is turned on.
Kernel rt1011 codec driver will read these device properties to set up
codec accordingly on boot.
The reason to prepare these parameters in coreboot is because kernel
codec driver expects to read per-device parameters directly from device
properties. Another benefit is that other OS can also take these
parameters through ACPI _DSD table and take benefit of DSM on RT1011.
The kernel driver device properties of RT1011 are documented at
linux/Documentation/devicetree/bindings/sound/rt1011.txt
It is currently in ASoC maintainer's tree at
https://kernel.googlesource.com/pub/scm/linux/kernel/git/broonie/sound/+/for-next/
and hopefully should be merged to mainline kernel in the next merge window.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On ChromeOS, there will be VPD values for dynamic speaker management (DSM)
calibration data. They are resistor calibration values and temperature
during calibration.
These VPD fields use "dsm_calib_" prefix.
Known keys are:
"dsm_calib_r0_0"
"dsm_calib_r0_1"
"dsm_calib_r0_2"
"dsm_calib_r0_3"
"dsm_calib_temp_0"
For now these values are unsigned decimal numbers greater than 0.
This library will be used for RT1011 device driver in the patch series.
Note that in the future we may encode more values into this VPD field if
needed. We retain the flexibility for coreboot device driver or codec
driver to decode/parse the VPD values based on the needed use case
per-board.
BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: Ib9579a5cc055f8f438cb30a8acaf250a343db19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Refactor I2C driver for fsp_baytrail to match the coreboot supported I2C
bus device structure. The internal I2C controllers are now handled by
the generic PCI driver approach and generic I2C access is enabled.
As orientation for the I2C code the actual solution from
soc/intel/apollolake I2C was taken. All the I2C specific parts were
removed from lpss.c and have been implemented in the I2C driver.
Future merge to soc/intel/common/block/i2c/i2c.c would be possible.
With this patch I2C chip devices can now be used in devicetree.
TEST=Booted siemens/tcu3 and verified that access to PTN3460 worked.
Change-Id: I3b87bd7c27e4c1afcce7cd4225cca02599f43c60
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
To allow retraining memory without hotkey (for example in manufacturing
process), we want to enforce re-training when the recovery reason is set
to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running
"crossystem recovery_request=0xc4").
The special reason was created for X86 MRC cache, for ensuring RO
calibration data is filled (the underlying implementation was in vboot,
not coreboot); and on MT8183 we have only RW calibration, but it seems
totally fine to extend that for RW.
BRANCH=kukui
BUG=None
TEST=boots; crossystem recovery_reason=0xc4; reboot
Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Use of typedef and modify the usage accordingly.
Change-Id: I875ef2fa31e65750233fa8da2b76d8db5db44f2d
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Use of typedef and modify the usage accordingly.
Change-Id: I65581702a60dbd286cb3910c6eeef5f9e1853cf1
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Currently only the PCIe ports 1-12 are checked for a wake event. Add
ELOG wake sources for ports 13-24, if they exist.
Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Similar to VMX and SMX also enable all GetSec leaves for Intel TXT.
Change-Id: I89620c2a98cfceaa785b1a798fafbf35cc99a0b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add code for FSP Broadwell DE to set the DPR.
Used by the Intel TXT code.
Tested on Intel Broadwell DE using Intel TXT.
Change-Id: Ib5e1ba8731e5cea1be9319a1fb9658dba841dc7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Lock AES-NI register to prevent unintended disabling, as suggested by the
MSR datasheet.
Successfully tested by reading the MSR on X11SSM-F
Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35188
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Avoid searching for cmos_layout.bin each time get/set_option is called
on platforms with NO_CAR_GLOBAL_MIGRATION.
Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The manifest example has to be marked as code. The Manifest parsing
section header should be L2 and finally # is a special character in
markdown.
Change-Id: I38cb1a508ec9ccb39cb39048de3742a5cb595f7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This adds another x11 series board, the X11SSM-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and
Ethernet interfaces.
Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
This code in reality just describes the southbridge features, don't put a copy
in every mainboard.
This commit follows up on commit e288758b with Change-Id
I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 ("bd82x6x: Merge common
platform ASL code").
Change-Id: Ic5260461165b794a13efd2c6d968c953f60dd253
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36229
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To fix MIPI D-PHY test failure, the hs-prepare should be less than
LimitMin from spec, and we have to enlarge TEOT margin.
BUG=b:138344447
BRANCH=kukui
TEST=Boots correctly on kukui
Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode.
VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted.
This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can
program related setttings to save power.
BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles
Change-Id: Ia02ff8823883489b36349457213409496f082f36
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The previous code actually set SlpS0WithGbeSupport even when GBE is
disabled in device tree and could cause power consumption in s0ix.
This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport,
PchPmSlpS0Vm075VSupport by device tree.
SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled.
BUG=b:134092071
TEST=Run suspend_stress_test on kohaku and pass 100 cycles
Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Commit 680027edf6 fixed a null dereference and logic bug in the tegra210
spi code:
soc/nvidia/tegra210: Fix potential NULL pointer dereference
Recent Coverity scan indicated potential NULL deference; if either
spi->dma_in or spi->dma_out are NULL, the fifo_error() check could
dereference a NULL pointer.
Also fixed what appears to be a logic bug for the spi->dma_out case,
where it was using the todo (count) from spi->dma_in.
Coverity is warning about the same problem for tegra124, so apply the
same fix there. Also, add braces around a while statement.
Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 124183, 124185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Autoport generates these structures as static so let's make it consistent.
This commit follows up on commit 6752b615 with Change-Id
I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for
const structures").
Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
This commit follows up on commit 9265f89f with Change-Id
I10b4300ddd18b1673c404b45fd9642488ab3186c ("arch/x86: Avoid
HAVE_SMI_HANDLER conditional with smm-class").
Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Change GPP_B21 default to low. This can prevent power leakage
of non-touch sku.
BUG=b:142849034
BRANCH=N/A
TEST=Measure the power of non-touch sku, check GPP_B21 is 0V.
Boot up with touch sku and check touch functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80a3e5dc224e4dab97c21fd469d8c3f2d3e774e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Configure enable pin GPP_D9 pull high when active
BUG=b:143046441
TEST=build bios and verify touch screen works fine
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I83060f31d4d22c9be05bba119816c6aa66e4126c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36186
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I446cd267dec2b6c0f7742a6834c7ee950528ad5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Elyes HAOUAS