Make psp verstage initialization more granular be splitting
verstage_soc_init into separate functions. Specifically, create
soc init functions for espi, i2c spi, and aoac.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add VBTs for all octopus variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Peppy's interrupts as Shared rather than the default
of Exclusive.
Test: build/boot Windows 10 on Peppy, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad in use.
Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This board does not have a LPC or eSPI connection to the NC FPGA anymore
and therefore IO port 0x80 is not useable for POST codes anymore. Enable
the feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visbile again in coreboot.
Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.
Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds cbfs_get_size() and cbfs_get_type() helper functions
(and _ro_ variations) to look up the size or type of a CBFS file without
loading it. Generally, use of these should be discouraged because that
tends to mean that the file needs to be looked up more than once, and
cbfs_alloc() or cbfs_type_load() are usually the more efficient
alternative... but sometimes they're unavoidable, so we might as well
offer them.
Also remove the <cbfs_private.h> header which had already become sort of
unnecessary with previous changes. cbfs_boot_lookup() is now exported in
<cbfs.h> for use in inlines, but should not be used directly by other
files (and is prefixed with an underscore to highlight that).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Initialize SPM (System Power Management) in RAM stage.
This adds 55ms to the boot time.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I822417f7a679107760b202dd43fb79d1934940bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM.
SPM needs its own firmware to enable SPM suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Setting of MSDC is defined by soc, so we move them to soc folder.
TEST=emerge-cherry coreboot; emerge-asurada coreboot
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.
TEST=build pass and check register ok
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch modifies the pch_get_ltt_value() function return type from
uint16_t to uint32_t to accommodate platforms with more than one thermal
threshold.
For example: Alder Lake PCH Trip Point = T2L | T1L | T0L
where T2L > T1L > T0L.
BUG=b:193774296
Change-Id: I5f46ccb457b9cfebf13a512eabb3fb0fab8adb39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.
TEST=Boot to OS, verify frequency locked.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Begin comments with # instead of ## to match the Makefile.inc generated
by spd_tools.
BUG=None
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In next phase build, the audio codec will change to ALC5682I-VS
BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This will enable preloading ramstage. By preloading the file into
cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush to OS and see 12ms reduction in boot time.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that CBFS has this functionality built in, we no longer need to
manually code it.
payload_preload used to use the payload_preload_cache region to store
the raw payload contents. This region was placed outside the firmware
reserved region, so it was available for use by the OS. This was
possible because the payload isn't loaded again on S3 resume.
cbfs_preload only uses the cbfs_cache region. This region must be
reserved because it gets used on the S3 resume path. Unfortunately this
means that cbfs_cache must be increased to hold the payload. Cezanne is
the only platform currently using payload_preload, and the size of
cbfs_cache has already been adjusted.
In the future we could look into adding an option to cbfs_preload that
would allow it to use a different memory pool for the cache allocation.
BUG=b:179699789
TEST=Boot guybrush and verify preloading the payload was successful
CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
eGPIO is a scheme which allows special power island domain IOs to be
reused as regular chip GPIOs by muxing regular TLMM functions with
Island Domain functions. Allow the eGPIO to be configured via
gpio_configure API to be used as a TLMM gpio.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
TEST=boot kernel from eMMC ok
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=boot kernel from eMMC and SDCard ok
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=build pass
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The _Static_assert without message string is only available
since C++17. Add the message to avoid build fail in the macro.
BUG=b:203145462
BRANCH=cherry
TEST=build pass and boot pass
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ib146ffafc21b9dbb9d383c9343a9ec1d7c478faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59298
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I49745948ebdb25fd98e285defd75714f80271968
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant
is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default
and only overriding to GPIO_70 for guybrush bid==1.
BUG=b:202992077
BRANCH=None
TEST=Build and boot guybrush, SD card works
Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
CPUCP is CPUSS Control Processor. It refers to the firmware for control
CPUSS active power management.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Redrix has 4 thermal sensors, so add the missing sensors settings.
BUG=b:200134784
TEST=build and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
As Hoglin variant was recently added, need to make sure that it uses
the same configs as piglin.
BUG=b:197366666
BRANCH=None
TEST=create hoglin image and make sure that it boots on CRD 2.0
Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59273
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are currently two users of the SPI hardware, the LPC SPI DMA
controller, and the boot_device_rw device. We need to ensure exclusivity
to the SPI hardware otherwise the SPI DMA controller can be interrupted
and it will silently skip transferring some blocks.
Depending on the SPI speed, this change might add a small delay when
clearing the elog since a DMA transaction might be in flight. I'll
continue optimizing the boot flow to avoid the delay.
BUG=b:179699789
TEST=Hack up the code to interleave SPI transactions and verify this
patch fixes the silent data corruption.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This method will allow preloading the VGA_BIOS_FILE. By preloading the
file, into cbfs_cache we reduce boot time. In the future we can also add
support for loading the second VGA_BIOS_FILE and the DGPU VGA_BIOS_FILE.
BUG=b:179699789
TEST=Boot guybrush to OS and verify 12 ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This change makes it so the timers run after each boot state callback,
and after each boot state. This gives coop threads the opportunity to
run more frequently and predictably.
BUG=b:179699789
TEST=Boot guybrush to OS, see SPI transactions progress faster.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This reverts commit adb393bdd6.
This relands commit 6260bf712a.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
With latest hardware revision all clock outputs will be used on this
mainboard. For this reason set all clock source mappings to
'PCIE_CLK_FREE' to have a free running clock.
Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
HECI #2 is not used for CSE communication. Therefore, it is not
necessary to set the parameter 'Heci2Enable' in devicetree.
Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
VT-d needs to disabled for early silicons as it results in a
CPU hard hang.
BUG=b:197177091
Test=Boot brya to OS with no hang
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
PCIE port 6 is empty as per schematics.
BUG=b:206047996
TEST=PCIE port 6 is disabled.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
USB2 port 0 is empty as per schematics.
BUG=b:206047996
TEST=USB2 port 0 is disabled.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table
is not called. Keep it unchanged.
Change-Id: I0e82188ce64733420a578446e22a077ef789be92
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
None of the *_DEVID defines was used in the code, so drop those. The SoC
code uses the PCI ID defines from include/device/pci_ids.h instead.
Since it might still be useful to have the PCI device IDs as a reference
in the SoC's pci_devs.h, add those as comments instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less
than 1, do not enable RTD3 driver.
BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3
no matter what the revision is for EWRD.
It will pass the WLAN driver check then to retrieve the data properly.
BUG=b:204414616
TEST= tested on brya with DRTU tool to verify if SAR table is
read properly or not.
Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8
Signed-off-by: Matt Chen <matt.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Rob Barnes