Commit Graph

41880 Commits

Author SHA1 Message Date
Arthur Heymans 89c5553d41 sb/intel/common: Implement acpi_is_wakeup_s3()
acpi_is_wakeup_s3() requires acpi_get_sleep_type().

Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07 06:06:34 +00:00
Kane Chen 3aee3ad46d soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
On tgl, we noticed system hang if a shutdown is triggered before fsps.
The dut is unable to shutdown properly due to tcss is stuck before
tcss_init in fsps.

This change enable power button smi on jsl, tgl, adl after fsps.
it can also prevent a shutdown failure due to lack of fsps init on
certain ip.

BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
     cause the system hang during shutdown.

Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07 06:05:37 +00:00
Kane Chen 7b7b33e3a6 soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
If a power button SMI is triggered between where it is currently
enabled and before FSP-S exits, when the SMI handler disables
bus mastering for all devices, it inadvertently also disables
the PMC's I/O decoding, so the register write to actually go into
S5 does not succeed, and the system hangs.

This can be solved by skipping the PMC when disabling bus
mastering in the SMI handler, for which a callback,
smihandler_soc_disable_busmaster is provided.

BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
     cause the system hang during shutdown.

Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07 06:05:18 +00:00
Martin Roth 4f27dde72a mb/google/mancomb: Update AMDFW config file
Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for
the LPDDR4 version. This changes to use SODIMMS.
Further changes may be needed for platform customization, so I put the
config file in variants/baseboard instead of the root mancomb directory.

BUG=b:187094481
TEST=Build only

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-07 02:54:22 +00:00
Martin Roth d233b1a831 mb/google/mancomb: Implement tis_plat_irq_status
This patch was implemented on Guybrush at CB:52352

BUG=b:185397933
TEST=Build

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I141a504a827f37724fab0aaed7498fd543e471d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06 23:40:56 +00:00
Martin Roth 804382343e mb/google/mancomb: Update Kconfig with needed options
DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not
used for the reset.
DRIVERS_UART_ACPI - Add the UART ACPI code
FW_CONFIG - Mancomb uses the firmware config interface
PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly
to send post codes to the EC, so disable them for now.

BUG=None
Test=Build

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06 23:40:30 +00:00
Martin Roth 8eefbe20d7 mb/google/mancomb: Fix EC SCI configuration
This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.
This same patch was added for Guybrush at CB:52673

BUG=b:186045622, b:181139095
TEST=Build

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 23:36:35 +00:00
Raul E Rangel 71c62ce69c mb/google/mancomb: Switch eSPI ALERT# to in-band
This matches what we are doing on guybrush.

BUG=b:187122344, b:186135022
TEST=build

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52956
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 23:32:20 +00:00
Raul E Rangel f33f857fbe mb/google/guybrush: Switch eSPI ALERT# to in-band
Using the push-pull alert was causing leakages when in S0i3. This is
because the EC drives ALERT#, so when the AP enters S0i3, the extra
current leaks into the SoC and ends up turning on the power regulators.
By using in-band ALERT#, the EC no longer drives this pin high, thus
fixing the leak. We could also have used an open drain alert, but the
rise time is less than ideal.

BUG=b:187122344, b:186135022
TEST=Measure S0i3 power on guybrush and validate it's no longer high.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-06 23:32:12 +00:00
Raul E Rangel 8317e727ce soc/amd/common/espi,mb/: Allow configuring open drain ALERT#
Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.

BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 23:31:26 +00:00
Raul E Rangel 6eced03b25 soc/amd/common/espi: Don't set alert pin in espi_set_initial_config
The eSPI spec says that the Alert Mode defaults to in-band on reset.
This change ensures the controller is in sync with the eSPI peripheral.

The configured alert mode is configured in
espi_set_general_configuration.

BUG=b:187122344, b:186135022
TEST=Boot guybrush and make sure we don't get any eSPI errors.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52953
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 23:31:19 +00:00
Raul E Rangel d2d762a4c9 soc/amd/common/espi: Print set eSPI peripheral config
This will print the config we are setting on the eSPI peripheral.

e.g.,
Setting general configuration: slave: 0x98a00000 controller: 0xe2000000
eSPI Slave configuration:
    CRC checking enabled
    Dedicated Alert# used to signal alert event
    eSPI quad IO mode selected
    Only eSPI single IO mode supported
    Alert# pin is open-drain
    eSPI 33MHz selected
    eSPI up to 20MHz supported
    Maximum Wait state: 0

BUG=b:187122344, b:186135022
TEST=Boot guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52952
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 23:30:55 +00:00
Raul E Rangel afe1fe55eb soc/amd/{common/picasso}: Move pci_int.asl
We can share this with cezanne.

BUG=b:184766519
TEST=Build picasso

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If746d55345f6b7c828376b64adc5532d20413f68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52916
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 23:27:50 +00:00
Raul E Rangel c8cfe7c8ff soc/amd/{picasso/common}: Move populate_pirq_data prototype to common
This method signature will also be used by cezanne, so move it to
common.

BUG=b:184766519
TEST=Build picasso

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I421bdad51776278f83148174e6f72bdc38249e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-06 23:14:12 +00:00
Raul E Rangel b3b1b25157 vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
This HOB describes the PCI routing table. It will be consumed by
coreboot to generate the _PRT ACPI object.

BUG=b:184766519, b:184766197
TEST=Build guybrush

Cq-Depend: chrome-internal:3794981
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-06 22:53:44 +00:00
Arthur Heymans 927be09559 emulation/qemu-x86: Select BOOT_DEVICE_NOT_SPI_FLASH
SPI flash is not emulated on these boards.

Change-Id: If29a87441cb26e53c9814ed10ddcfe14752c3965
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52791
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 19:05:16 +00:00
Angel Pons ca5d3e3b2b drivers/pc80/rtc/option.c: Constrain API to integer values
None of the options accessed within coreboot is a string, and there are
no guarantees that the code works as intended with them. Given that the
current option API only supports integers for now, do not try to access
options whose type is 's' (string).

Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06 14:49:10 +00:00
Angel Pons 88dcb3179b src: Retype option API to use unsigned integers
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.

Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-06 14:48:15 +00:00
Subrata Banik a2cf34129f include/console: Align ramstage Boot State Machine postcodes
This patch ensures all boot state machine postcodes are in right
order. Move POST_ENTRY_RAMSTAGE macro definition after
POST_BS_PAYLOAD_BOOT.

Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 14:39:06 +00:00
Michał Żygowski 88a0ce6e11 nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
Do not use get_dram_base_mask to calculate system DRAM limits. Shift
operation around values operating on base and mask were causing
overflows and thus incorrect system DRAM limit. Another function
returning base and limit in KiB has been developed to avoid data loss.

Keep DRAM high base and limit in calculations only for Trinity where
the physical CPU address bits is 48. Although it is almost impossible
to have a non-zero value there, the platform would have to support
nearly 256GB of RAM.

TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian
with Linux 4.14

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-06 14:38:04 +00:00
Tony Huang 9c9844922c mb/google/octopus: add audio codec into SSFC support for Bloog
BUG=b:186380809
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.

Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2021-05-06 14:36:45 +00:00
Bernardo Perez Priego e73e1ce9de mb/intel/adlrvp_m: Disable Type-C xDCI
Disabling this pci 0d.1 device since it is not required.

TEST= Boot to OS.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52744
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 14:36:01 +00:00
Arthur Heymans 50ece62d3c arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"
Tested on qemu/i440fx on X86_64:
- Page tables are found in cbfs (finding a file works)
- returns 0 when a file is not found
- works when there is no cbfs file at the start of the FMAP, e.g. with
  the cbfs master header removed.

Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52879
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 14:34:51 +00:00
Arthur Heymans a033d8c808 arch/x86: Always include walkcbfs.S
Let the linker decide if this code is needed.

Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06 14:31:52 +00:00
Jason Glenesk 4e3658fd57 mb/amd/majolica: Enable S0i3 by default
Set s0ix_enable to true.

BUG=b:178728116
TEST=Cold boot and perform a cycle of S0i3.

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-06 14:27:53 +00:00
Arthur Heymans a1c4ad38d5 Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"
This reverts commit 8122b3f612.
This broke DMAR. DRHD defines the scope of the device entries below.

Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-06 09:10:30 +00:00
Arthur Heymans 6f8e9443aa security/tpm: Add option to init TPM in bootblock
When using a hardware assisted root of trust measurement, like Intel
TXT/CBnT, the TPM init needs to happen inside the bootblock to form a
proper chain of trust.

Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51923
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 08:26:41 +00:00
Tim Wawrzynczak 59a621abc7 soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.

BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:59 +00:00
Tim Wawrzynczak 6dc72022a5 soc/intel/tigkerlake: Add IOM PCR PID
Required for accessing IOM REGBAR space.

Change-Id: Ic1c9beee69d184388f3e850744b3aeebe38eafbb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:49 +00:00
Tim Wawrzynczak a137201edd soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities
Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:41 +00:00
Tim Wawrzynczak 87b7ec2ebb soc/intel/common: Add CPU Port ID field to GPIO communities
The CPU can have its own Port IDs when addressing GPIO communities, which
differ from the PCH PCR IDs.

1) Add a field to `struct pad_community` that can hold this value when
   known.
2) Add a function to return this value for a given GPIO pad.

Change-Id: I007c01758ae3026fe4dfef07b6a3a269ee3f9e33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:32 +00:00
Tim Wawrzynczak 8d3cc1bcc2 soc/intel/tigerlake: Add known GPIO virtual wire information
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at
least some of their groups; add the known information into the community
definitions.

Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 04:12:13 +00:00
Tim Wawrzynczak 629ddfd265 soc/intel/common: Add virtual wire mapping entries to GPIO communities
Some SoCs may define virtual wire entries for certain GPIOs. This patch
allows SoC code to provide the mappings from GPIO pads to virtual wire
indexes and bits when they are provided. Also a function
`gpio_get_vw_info` is added to return this information.

Change-Id: I87adf0ca06cb5b7969bb2c258d6daebd44bb9748
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52588
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 04:11:59 +00:00
Francois Toguo cea4f92e4a soc/intel/alderlake: Add CrashLog implementation for Intel ADL
This enables CrashLog for Intel ADL based platform.

BUG=b:183981959
TEST=CrashLog data generated, extracted, processed and decoded sucessfully on adl-m RVP.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I15ba0b41f73c1772f09584f13bcf5585caa90782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52454
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 03:32:22 +00:00
Arthur Heymans ee85d00ed6 util/intelp2m: Set GO111MODULE environment parameter explicitly
With go1.16 the default for GO111MODULE changed to on which break
building this tool.

Change-Id: I93a516ff76c8da4b7f37157d58ecd4c0b09c582c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52862
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 22:46:18 +00:00
kirk_wang c33e2dc626 mb/google/dedede: Create pirika variant
Create the pirika variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:184157747
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_PIRIKA

Signed-off-by: kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52626
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 22:42:38 +00:00
Maulik V Vaghela e6e8b3d337 soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
Adding GPIO definition for community 3 which is CPU reserved GPIO used
by CPU side PCIe root ports. We did not have this definition since
FSP used to program this GPIOs. Now, instead of FSP, coreboot programs
CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode.
Thus adding definition of this virtual GPIOs in this CL.

BUG=None
BRANCH=None
TEST=Check if correct registers are being programmed

Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-05 22:41:41 +00:00
Maulik V Vaghela cc3637f177 soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg
Earlier we did not have definition for BIT27 for PAD_CFG0 register, we
will use this BIT to enable "virtual wire messaging for native function"
If this bit is enabled, whenever change is detected on the pad, virtual
wire message is generated and sent to destination set by native function.
This bit must be set while enabling CPU PCIe root port programming for
ADL and thus defining a new macro to set native pad function along with
NAF_VWE bit to make GPIO programming easier from coreboot.

BUG=None
BRANCH=None
TEST=Code compilation works fine and if we use this macro to program
GPIO, proper bit is getting set in PAD_CFG register

Change-Id: I732e68b413eb01b8ae1a4927836762c8875b73d2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52782
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 22:40:44 +00:00
Karthikeyan Ramasubramanian c616fd5b7a mb/google/guybrush: Configure Pen Detect device
Pen Detect GPIO is exported through GPIO keys driver to the kernel so
that stylus tools is popped on pen eject event. Hence enable the GPIO
keys driver and configure the devicetree.

BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is
added to the ACPI SSDT table. Ensure that the Pen Eject events are
detected.
Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1620159356.243180, -------------- SYN_REPORT ------------
Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Ensure that when the device is suspended, it wake on Pen Eject event and
does not wake on Pen Insert event.

Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05 22:38:56 +00:00
Felix Held 8143d03d51 soc/amd/cezanne/agesa_acpi: add add_agesa_fsp_acpi_table call
this adds the ALIB SSDT that gets passed from the FSP to coreboot via a
HOB.

BUG=b:185481298

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a7dae5789eee442b321ddf276494eb53fc5f499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-05 21:43:34 +00:00
Anil Kumar 88dd4f705a mb/intel/adlrvp: Enable support for Chrome OS mode switches
Branch=none
Test=build and boot ADL-M RVP. Test recovery mode using servo command
dut-control power_state:rec

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52614
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 20:27:13 +00:00
Tim Wawrzynczak 54c3662a57 util/sconfig: Fix null pointer dereferences
Should use `name` instead of `field->name`, because `field is supposed
to be NULL at this point.

TEST=add new field from bits 29-64 to volteer, ensure sconfig prints an
error instead of segfaulting.

Change-Id: I933330494e0b10e8494a92e93d6beb58fbec0bc1
Found-by: Coverity CID 1452916
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52888
Reviewed-by: Duncan Laurie
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 20:26:38 +00:00
Felix Held cdae2d9cdf vc/amd/fsp/cezanne/FspGuids: add AMD_FSP_ACPI_ALIB_HOB_GUID
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I531c8e8d0ee2aa72b51cba59e09e7a7d253da4f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-05 19:39:35 +00:00
Felix Held 144c7aa34b soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables
This function will be used to add some SSDTs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-05-05 19:39:22 +00:00
Felix Held afc4978ede soc/amd/picasso/agesa_acpi: add comment to add_agesa_fsp_acpi_table call
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I409993dcecd38bd2ad603ba467b299a6eab177ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52901
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 19:39:01 +00:00
Felix Held f3e268bc3b soc/amd/picasso/agesa_acpi: add missing device/device.h include
agesa_write_acpi_tables has one struct device parameter.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7892cf680661253f74c3e291f5e9fb372e1d4ce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-05 19:38:50 +00:00
Felix Held 75a2355a19 soc/amd/common/fsp/fsp-acpi: add check for maximum table size
If the ACPI table size in the HOB data header is larger than the maximum
HOB payload, don't add the table at all and print an error instead,
since in this case the memcpy would read past the end of the HOB data
structure.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I965c01bd9ab66b14d6f77b6f23c28479ae6d6a50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52897
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 18:35:29 +00:00
Felix Held 245adcab13 soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionality
This function will be reused in Cezanne, so move it from the Picasso
directory to the common FSP integration code.

TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-05 18:35:20 +00:00
Raul E Rangel 3cb69c2397 mb/google/guybrush: Fix S0i3/S3 GPIO configuration
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.

BUG=b:186011392
TEST=Wake system from S0i3 with EC and see GPE 3 increment.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05 15:31:07 +00:00
Arthur Heymans 0f068a600e drivers/intel/fsp2_0: Fix the FSP-T position
The only use case for FSP-T in coreboot is for 'Intel Bootguard'
support at the moment. Bootguard can do verification FSP-T but there
is no verification on whether the FSP found by walkcbfs_asm is the one
actually verified as an IBB by Bootguard. A fixed pointer needs to be
used.

TESTED on OCP/Deltalake, still boots.

Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-05 15:14:46 +00:00