Support memory range querying to above/below 4GiB.
Enable PRERAM_CBMEM_CONSOLE.
BRANCH=none
BUG=none
TEST=build and verified pass on oak board
Change-Id: If12ab2e9b8a129e2c82dd97b0493d9abdd6985a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 139a3163ca867ec5676c6cb81fdec724c99a4a99
Original-Change-Id: Ie190f86f49ae88671f0738e2d6ceafdad58a93cc
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292559
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55
Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313969
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13097
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=build pass and test it ok on oak
Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23
Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292687
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13095
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=test it ok on oak-rev3
Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4
Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297942
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=build and verified pass on oak board
Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8
Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292683
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13091
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S.
The function is called by mainboard's configure_audio().
BRANCH=chromeos-2015.07
BUG=chrome-os-partner:41507
TEST=build and verified pass on oak board
Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6
Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297225
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13090
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=none
Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0
Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292677
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12617
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The mt8173 boot rom expects the bootblock to be in a certain format.
gen-bl-img wraps our bootblock appropriately.
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3
Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292664
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for verstage
[pg: split original commit into multiple commits]
Change-Id: Ia43bc72a1fb36c6fad5be5654abee5fc19fc4093
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
[pg: split original commit into multiple commits]
Change-Id: I0dc8d9855c98c077d4a47227de0c504c3a846953
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Don't select SPI_ATOMIC_SEQUENCING unless SPI_FLASH is being used.
warning: (... SOC_MEDIATEK_MT8173) selects SPI_ATOMIC_SEQUENCING
which has unmet direct dependencies (SPI_FLASH)
Change-Id: I93e9a7102d1d0ef62565110b5b3b677da8d0c72b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=chromeos-2015.07
BUG=none
TEST=verified on Oak rev3
Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f
Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297224
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE
from SRAM_L2C to ensure that it can be switched correctly.
BRANCH=none
BUG=chrome-os-partner47952
TEST=none
Change-Id: I255a0116148777d384dda43682365a5e2375cb5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792
Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313888
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12602
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
