Commit Graph

767 Commits

Author SHA1 Message Date
Peter Stuge 8a681b1d84 flashrom: Provide some hints for the user in case /dev/mem mmap fails.
resolves #121

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-22 22:53:59 +00:00
Stefan Reinauer 269563a423 First shot at factoring SMM code into generic parts and southbridge specific
parts.

This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19 21:20:22 +00:00
FENG yu ning 0fd183ce72 flashrom: Fix ICH9 locking register address and add important debug output.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-18 06:39:32 +00:00
Peter Stuge 884e1cbeeb flashrom: Add ICH opcode debugging.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 02:13:18 +00:00
Stephan Guilloux d860763e73 Similarly to flashchips array, this patch intends to make the table
board_pciid_enables more readable.

Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>

> What real problem does this solve?

1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.

The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 00:48:24 +00:00
Peter Stuge 3462462b2a flashrom: Always print address when verification fails, not only with -V.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-13 14:32:27 +00:00
Peter Stuge e31a8d5c95 flashrom: Board enable for GIGABYTE GA-MA78G-DS3H
This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 21:31:14 +00:00
Peter Stuge 88ded318c3 flashrom: IT8718F works just like IT8716F.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 21:28:03 +00:00
Peter Stuge 475ac26a9b flashrom: Check return value of fscanf()/fwrite()/fread()
Fix build error on distros with warn_unused_result attributes in glibc.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 21:00:35 +00:00
Idwer Vollering 6fa7e6dae9 flashrom: Update usage in README
Mimicked from flashrom.c

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-11 03:31:02 +00:00
Carl-Daniel Hailfinger 0afdea4e42 Add erase and write functions to the following chip definitions:
AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641
AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321
AT26F004

Straight from the data sheets, untested because I lack the hardware.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08 16:53:13 +00:00
Carl-Daniel Hailfinger 44b3bf7ed7 The flashrom man page has incomplete author/copyright sections and an
incorrect license section.
- Remove the copyright listings and refer the reader to the source
  files.
- Update the author list to those which have copyright messages in the
source files.
- Correct the license from GPL v2+ to (GPL v2, with some files under
  later versions as well)

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08 04:56:59 +00:00
Stephan Guilloux 901f25acd3 This patch improves machine parseability and human readability of
flashchips.c over what's currently in flashrom HEAD.
The explicit initialization makes sure any future struct flashchip
reordering is not needed. (Except for the case where we need arrays
of some of the struct members.)

Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08 03:40:17 +00:00
Sven Schnelle d32b9e605f Add SST49LF020 support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:35:09 +00:00
Sven Schnelle f58691ffb6 Add AMD-768 chipset support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:15:46 +00:00
Sven Schnelle c84ce73ab8 Add i631x LPC support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:11:13 +00:00
Uwe Hermann 29fbb761ec If you pass a bogus layout file to the -l option flashrom will segfault.
Fix that by throwing an error instead.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:42:59 +00:00
Uwe Hermann fdc5470bcf Add another board-enable line for the Kontron 986LCD-M/mITX.
There seem to be at least two versions of the board out there, and the
subsystem IDs changed between the versions.

Patch successfully tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:40:45 +00:00
Peter Stuge 3071acf370 flashrom: Initialize ICH SPI opcodes also for ICH9 and later.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 14:12:08 +00:00
Michał Mirosław eb390abb4e This adds register map based on NSC PC87392 datasheet. LDN#2 can be
used for a SIR/FIR device.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Ulf Jordan <jordan@chalmers.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20 19:35:54 +00:00
FENG yu ning a8faa2a479 * add a generic preop-opcode-pair table.
* rename ich_check_opcodes to ich_init_opcodes.

* let ich_init_opcodes do not need to access flashchip structure:
  . move the definition of struct preop_opcode_pair to a better place
  . remove preop_opcode_pairs from 'struct flashchip'
  . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure

* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.

* fix a coding style mistake.

Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15 02:32:11 +00:00
Carl-Daniel Hailfinger b3b2804482 Add 28 flash chips of the MX29 series to the flashrom ID table and
support the MX29LV040C.

MX29LV040C probe and read support tested by khetzal on IRC.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10 10:32:05 +00:00
Carl-Daniel Hailfinger 17da8d706f Kill obsolete and misplaced comment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 23:51:45 +00:00
FENG yu ning 8a07f703ec Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI
configuration is locked down.

Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 18:16:58 +00:00
FENG yu ning 60e7eebf96 Breaks chip info into multiple lines.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 18:15:10 +00:00
Peter Stuge baada5efaf flashrom: Display test status in -L chip listing
Looks like this:

Supported flash chips:          Tested OK operations:   Known BAD operations:

AMD Am29F002(N)BB                                       
AMD Am29F002(N)BT               PROBE READ ERASE WRITE  
AMD Am29F016D                                           
AMD Am29F040B                   PROBE READ ERASE WRITE  
AMD Am29LV040B                                          
Atmel AT45CS1282                                        READ 

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-06 01:37:09 +00:00
Niels Ole Salscheider 24788351dc flashrom: Add AMD SB700 flash enable
This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 11:58:43 +00:00
Peter Stuge 5a0be5193e flashrom: Fix compilation of r3797 with gcc-4.3.2
Thanks to Niels Ole Salscheider for the problem report.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 11:56:57 +00:00
Peter Stuge b4b56e669b flashrom: Check if erase succeeds and exit with error on failure.
flashrom used to exit 0 even if erase failed. Not anymore.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 02:22:30 +00:00
Stefan Reinauer 1162f25a49 Patch to util/inteltool:
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 15:18:20 +00:00
Carl-Daniel Hailfinger fcf9be3b93 Add RDID/REMS IDs for the following flash chips:
SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 00:58:10 +00:00
Peter Stuge fd5a2df876 flashrom: gcc thinks base could be used uninitialized, so shut it up.
Bug from r3791.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 23:36:48 +00:00
Peter Stuge 9602d1e828 flashrom: Fix bug in r3790
If flashbase was set before probe_flash() it would only ever be used once, for
the very first flash chip probe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:39:56 +00:00
Stefan Reinauer d53f3e7546 Replace #ifdefs for sc520 systems by run time probing.
fixes #109

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:24:40 +00:00
Stefan Reinauer b9b500f456 build_opt_tbl:
make sure the temporary files are created in the same directory as the
target files so they can be rename()d. This fixes a compilation issue on
machines with the build directory living on another partition than /tmp.
Pretty trivial.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02 12:26:17 +00:00
Stefan Reinauer 7a51e50582 The Winbond Super I/O chips have another indirection of registers. The
hwmon has generic registers and banked registers, mostly temperature
handling, and SMI/GPIO stuff.

Not all LDNs are switched via register offset 0x07, make it a parameter.
  
Add support for dumping the hardware monitor of Winbond W83627THF/THG
parts with the -e option.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 14:18:57 +00:00
Stefan Reinauer b4eb4fb6b0 ok, another attempt to the build_opt_tbl problem:
- create temp files and move them afterwards
- remove dummy option -b
- fix usage
- drop implicit creation of .c file if no --option is specified.

Now let's see if this fixes the issue. :-) We don't want to take 24s
instead of 6s to build an image reliably (Yes, yes, I know Tiano takes
over 20 minutes)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-30 14:52:46 +00:00
Jason WangQingpei.wang 70a1f735a9 Copyright update by Jason Wang for freshly written sb600 code.
Signed-off-by:  Jason Wang<Qingpei.wang@amd.com>
Reviewed-by:    Joe, Bao <Zheng.Bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-29 15:07:15 +00:00
Carl-Daniel Hailfinger 8b30d5d298 Declare special commands to support the Atmel AT25F512A.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:47:55 +00:00
Carl-Daniel Hailfinger f86f1fe961 If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:45:27 +00:00
Jason Wang f22ce41840 Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.

Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 21:36:51 +00:00
Stefan Reinauer 38bee3c8b6 This patch fixes the ugly race condition created through build_opt_tbl
running twice at the same time, overwriting its output files. This caused
a depending rule to produce an object file with no symbols in it.

This should silence up the regularly happening build failure messages on
the mailing list since we moved to the newer, much faster server.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 11:56:27 +00:00
Jason Wang d95e43cc8f Add SST25VF080B flash chip support.
This is the first chip which uses the infrastructure for alternative
erase commands, namely spi_chip_erase_60_c7().

Signed-off-by:  Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by:   Joe Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 05:40:27 +00:00
Carl-Daniel Hailfinger 6f24cbc083 Flashrom already has the following probe functions:
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID

RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.

The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 01:25:00 +00:00
Carl-Daniel Hailfinger c88733c021 The existing check in probe_spi_res() was right for SPI controllers
which support all commands, but may not exist.
For controllers which support only a subset of commands, it will fail in
unexpected ways. Even if a command is supported by the controller, it
may be unavailable if the controller is locked down.

The new logic checks if RDID could be issued and its return values made
sense (not 0xff 0xff 0xff). In that case, RES probing is not performed.
Otherwise, we try RES.
There is one drawback: If RDID returned unexpected values, we don't
issue a RES probe. However, in that case we should try to match RDID
anyway.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-27 22:48:48 +00:00
Peter Stuge 0924dee124 msrtool: Use libpci to let system and target probes find PCI devices.
And some more notes in TODO.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-25 02:03:16 +00:00
Tero O Peippola ef8ea01c8c Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli.
File util/flashrom/flash.h already had correct ID for that part.

Signed-off-by: Tero O Peippola <xeropp@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-24 20:23:23 +00:00
Peter Stuge cc9db9dfa0 msrtool: Very small fixes I made after sending out the rc1 tarball.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22 18:29:44 +00:00
Peter Stuge dad1e3091f msrtool: Release Candidate 1
msrtool can decode MSRs and print the value of every field in human
readable form. It can also be used to save a set of MSRs to a file,
and at a later time compare the saved values with current values in
hardware.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22 17:13:36 +00:00
Carl-Daniel Hailfinger 8c0702b89b Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:43:14 +00:00