edk2's default is to show a Boot Splash with their own logo which
looks like it's from the 1960's. Therefore, we replace this image
with coreboot's logo, taken from https://coreboot.org unless a
custom one is specified.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b133e2a2cfd45a6650e4523b267f7508974137b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Set GPE route as
GPE0_DW0 -> GPP_A
GPE0_DW1 -> GPP_E
GPE0_DW2 -> GPP_F
BUG=b:224325352
TEST=Verified in emulator that there is no regression
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5e3e09cfc06d2556ea32cca23b3dae114a510498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This reverts commit b57d172fbb.
Reason for revert: Results into hard hang with serial debug msg as
below:
`[EMERG] Unable to unhide the P2SB device!`
Intel team is working towards to fix this issue.
BUG=b:239806774
TEST=Able to boot the Intel/MTLRVP with this revert.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic6be37c000afdf4f0c6c22497c233aa0bbc49d48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65500
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides `Lp5CccConfig` UPD as per the CCC mapping data
captured from the Rex schematics dated 07/16.
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia1d9e3665cff74a803e730c76f62773996efb3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR config on Meteor Lake
to instruct Pad Configuration Lock.
BUG=b:211573253, b:211950520, b:213596994
TEST=Able to perform GPIO lock programming without error on MTLRVP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icd123adb02716149fa51c9e4c987c281f9de2f43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Add the required files to support VBOOT for when it is enabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The X2APIC_LATE_WORKAROUND kconfig allows bringing APs in XAPIC mode initially hence, it won't work if LAPIC ID is > 0xff.
This patch ensures the MAX_CPUS logic is appropriate while selecting X2APIC_LATE_WORKAROUND kconfig from SoC.
BUG=b:219061518, b:219053812
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I466e6cc568024a9dea80af21e0ebf3572e74a1f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add pujjo new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Micron MT62F1G32D4DR-031 WT:B
BUG=b:239776504
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch updates the GPIO lock configuration recommendation
kconfig string to ensure the SoC user can select the correct
config as applicable for the SoC.
Note: From MTL onwards GPIO lock config can be performed using
PCR write (MMIO write) and the GPIO team has confirmed this.
BUG=b:213596994
TEST=Able to fix below GPIO lock config error msg on MTL with
`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR` kconfig enabled.
[INFO ] Locking pad configuration using SBI
[INFO ] gpio_pad_config_lock_using_sbi: Locking pad 73
configuration
[ERROR] SBI Failure: Transaction Status = 1
[ERROR] Failed to lock GPIO PAD, response = 1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icab1e4849b8e08ee1c695c924599f1513774178f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch ensures the debug consent value is matching with the
inline comment.
TEST=Able to build the Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icf72eb2aa4064fd78f4f99570a4cf44e41932ec3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66008
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus,
integrate it into lenovo/haswell and make it a variant.
Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
In preparation to CB:63514, make the INT15 support specific for the
T440p variant since the W541 doesn't support it currently.
Change-Id: I8dfcc061e1b8a831f75bf9a8035770cb678a85d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds more GBB related configs. Select
`HAS_RECOVERY_MRC_CACHE` config.
Additionally, move VBOOT_LID_SWITCH config under VBOOT config.
TEST=Able to build the Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Hide these ACPI device so Windows does not warn about missing device
drivers.
Change-Id: Iba6cf7a17eefc9f4f247621f6625151f2fd5f3a7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set the default value for MAX_CPUS in the SoC config and drop it from
the mainboards where it is set to those values.
Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use fw_config Bit 0 and Bit 1 to control:
Bit 0 = 0 --> enable WFC
Bit 0 = 1 --> disable WFC
Bit 1 = 0 --> enable pen garage wake
Bit 1 = 1 --> disable pen garage wake
BUG=b:238045498
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Remove the sections that coreboot doesn't need to know about.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 58f68fb0cb.
Reason for revert: ODM thermal team request that change IA/GT TDC
current back to 20A.
BUG=b:237230877
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read
board_id() on rex.
TEST=Verified builds succeed and code is linked
Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Geralt reference design has both eMMC and SD card interfaces, so we
configure both in mainboard_init() in ramstage.
TEST=boot to kernel using emmc successfully.
BUG=b:236331724
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I200a065ab96584d824153480e594e19baae97f9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65976
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Geralt reference design has both eMMC and SD card interfaces, so we have
to configure both in ramstage.
Implement msdc.c (mass storage device class) to place the eMMC and SD
card drivers.
This implementation is based on chapter 5.9 in MT8188 Functional
Specification.
TEST=boot to kernel using emmc successfully.
BUG=b:236331724
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We plan to make 3 firmwares which differ only by Kconfig options and
can share a common variant directory.
ghost4adl: Board with an ADL chip.
ghost4es: Board near identical but has RPL-ES chip.
ghost: Will have final RPL silicon.
Since they will only differ by Kconfig options and Intel binary blobs,
let's not duplicate the variant directory but instead share it in
common.
BUG=b:239456576
BRANCH=firmware-brya-14505.B
TEST="make menuconfig", verify layout of board selection
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and
set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli.
BUG=b:218985167
TEST=emerge-brask coreboot and check RTL8111K LED behaviour
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
While adequate for ChromeOS, 16MiB VRAM is insufficient for current
mainline Linux and Windows amdgpu drivers to operate properly. Under
Linux, the driver fails to allocate a framebuffer and causes multiple
kernel panics. Under Windows, the driver fails to load due to
insufficient resources available. Revert the VRAM allocation to the
previous amount of 32MiB.
This change reverts
commit 87dcd0061a ("mainboard/google/kahlee: Reduce VRAM to 16MB")
Test: build/boot Linux 5.17.x on google/liara, verify framebuffer
allocation succeeds and no kernel panic reported.
Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b
Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The full dGPU power-on sequence, when executed from ACPI, is taking
roughly 15ms or so, which puts it close to the maximum of 20ms required
from the Nvidia spec. Changing the polling period to 100 us instead of 1
ms drastically reduces the time required for this sequence, now taking
typically 7 ms or so. This gives a lot more margin during the power on
sequence.
BUG=b:238466724
TEST=Sequence verified by EE on a scope
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Zoglin is like Hoglin, but with a smaller flash size, which requires
us to create a new variant.
BUG=b:239851866
BRANCH=None
TEST=Make sure BOARD_GOOGLE_ZOGLIN builds
Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change
sets it.
BUG=b:239628052
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot" and verify that the following configs
are set as:
CONFIG_BOARD_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB=32768
CONFIG_ROM_SIZE=0x02000000
Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the white hare coreboot logo in Documentation so that it can be
used for various things, including the bootsplash for edk2.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3a1d64cc3bf695f88e163eda96e03b841ad04a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65931
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because 0 and 1 are the only possible values,
1. Change input argument "enable" of mainboard_enable_regulator to bool.
2. Change return value of mainboard_regulator_is_enabled() to bool.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8188, we need to enable and adjust VMCH and VMC to support SD
cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs.
TEST=measure 3.0V in VMCH and VMC.
BUG=b:236331724
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PMIF, SPI, SPMI and PMIC init code.
These PMIC settings are used by MediaTek internally. We can find these
registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and
"MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek
designers.
TEST=build pass
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We will use the same drivers for checking ulposc in MT8188, so we add a
new function pmif_ulposc_check() to common.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ti50 hasn't implemented version reading yet. To avoid the confusing
error message
Did not recognize Cr50 version format
enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this
feature is not supported.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Sean Rhodes