Commit Graph

35131 Commits

Author SHA1 Message Date
Brandon Breitenstein b7911c8e98 mainboard/volteer: Update Aux settings for Port 0
On Volteer port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping. This
requires 2 changes setting the TcssAuxOri UPD to 1 for port 0 (Bit 0)
and configuring AUXP and AUXN GPIOs to Native Function 6 so SOC can
control the orientation

BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped

Change-Id: Ic81adc24d10322cc305bf0fa4c38514468ea0942
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-20 09:13:27 +00:00
Brandon Breitenstein 71d365d458 soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg
In order for the SOC to be able to control the Aux line orientation for
Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs
to be configurable through devicetree to correctly set the GPIO pins that
the SOC should use to flip orientation.

BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped

Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 09:13:16 +00:00
Caveh Jalali b9907042d4 mb/google/volteer: Enable EARLY_EC_SYNC
This enables EC software sync in romstage.

BUG=b:148259137
TEST=verified EC is updated in romstage using coreboot serial console
	logs.

Change-Id: Ibb97c1d57220f7fd74131a5aee450b1ab4b1c982
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41078
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 09:12:58 +00:00
Eric Lai af417b4143 mb/google/deltaur: Remove WLAN PCIE setting
Deltaur uses CNVi WLAN module, this setting is not required.

BUG=none
TEST=WiFi is functional in OS.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-20 09:12:36 +00:00
Eric Lai 38c308515c mb/google/deltaur: Add tcss.asl
Add tcss.asl to support TCSS power management.
For the detail please refer cb:39785.

BUG=none
TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3
     /sys/bus/pci/devices/bus:device:func/power suspend and
     active time can increase.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 09:12:28 +00:00
Aamir Bohra 88712991ba soc/intel/jasperlake: Add ACPI method to get GPIO PCR PID
Add method acpi method GPID to return the GPIO PCR port ID.
This method is further planned to be used for GPIO power
management configuration.

TEST=Build waddledoo board

Change-Id: Ic45b40bbe39e303cddcc82e0e848786b7311ab64
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-20 09:11:51 +00:00
Aamir Bohra a2789328f7 soc/intel/common/acpi: Remove gpio community range
Remove hardcoded gpio community range, since it might differ across
the SOCs.

Change-Id: I79c10669f6096537d466d1abd356d58a50fcb8f5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-20 09:11:40 +00:00
Seunghwan Kim 8952de55cb driver/i2c/max98390: Fix build error related to max98390 driver
Fix coreboot build error with adding this driver

BUG=b:149443429
BRANCH=None
TEST=built without errors

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I2d76ec72ca6ae9ac54ab05f15ea92beb645acd5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20 09:11:23 +00:00
Eric Lai 40d00ddcf2 mb/google/deltaur: Add low power idle table
Add low power idle table to notify EC system is entering s0ix.

BUG=none
TEST=Power button and keyboard backlight are off when suspending.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icf4dffe2bd289c15854bbad914c3b34b307254ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41494
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 09:02:29 +00:00
Patrick Georgi 030037d3e9 superio/winbond/w83977tf: Scope UART configuration defines more locally
By undefining the configuration after use we're sure that nobody else
comes to depend on it without us noticing.

Change-Id: I7c5cfd58be643d6431989fc69cf3b397920590b9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-20 08:44:36 +00:00
Patrick Georgi 736024afdb Documentation: Encourage documentation with code changes
The resource allocator woes post-4.12 release showed room for
improvement on both discussion and documentation.  To encourage this
(and encourage reviewers to look out for issues in that space),
extend the review guidelines so that they encourage to more clearly
document the reason for a change with the change (commit message or
our documentation) and also to loop in the mailing list.

Change-Id: I1962dba3fe7e1a01fa4c8b0058297c7d050cb7b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-20 08:44:26 +00:00
Edward O'Callaghan 64e15aac1b mb/google/hatch: Fix Puff variants rom size from 32768 -> 16384 KB
Originally variants make use of a 32MB chip whereas now they
use a 16MB SPI flash. Allow for the coordination of dealing
with the transition between phases.

V.2: Leave Puff alone at the moment due to the complexity of
     coordination.

BUG=b:153682192
BRANCH=none
TEST=none

Change-Id: Ic336168ea1a0055c30f718f5540209d2cf69d029
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40897
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 01:11:17 +00:00
Furquan Shaikh 66b9c0efb5 soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.

This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.

Change-Id: I11b3ef8deda21930998471ab6e712da4c62f5b02
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-20 00:35:25 +00:00
Furquan Shaikh 6dc858a01f soc/intel/broadwell: Update systemagent.asl to ASL2.0 syntax
This change updates systemagent.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for auron.

Change-Id: I479bb6cb7ed4c9265325c7c8621f03454f21f467
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-20 00:35:17 +00:00
Furquan Shaikh 01750ef8d7 soc/intel/skylake: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.

This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.

Change-Id: I2ff7a30fabb7f77d13acadec1e6e4cb3a45b6139
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-20 00:35:10 +00:00
Furquan Shaikh c336130c44 soc/intel/skylake: Update systemagent.asl to ASL2.0
This change updates systemagent.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for soraka.

Change-Id: If8d8dd50af9a79d30f54e98f7f2fe7ce49188763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-20 00:35:03 +00:00
Furquan Shaikh 5434deaf2a soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL
was incorrectly updated to use << (ShiftLeft) instead of >>
(ShiftRight). This change fixes the error in GPCL by updating it to
use >> (ShiftRight).

TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for hatch.

Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 00:34:43 +00:00
Marshall Dawson eb72487784 soc/amd/picasso: Add pcie root complex driver
* Declare memory and reserved areas using HOBs for regions above top
  of low memory.
* Copy northbridge_fill_ssdt_generator from stoneyridge.

BUG=b:147042464
TEST=Boot trembyle and see PCI resources in the log:
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
   PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4
   PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5
   PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6
   PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7
   PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8
   PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9
   PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a

Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 00:31:01 +00:00
Martin Roth 49b09a06a9 soc/amd/picasso: Add Kconfig option for the PSP bootloader filename
Add option to change bootloader file.

BUG=b:149934526
TEST=Change option and verify new bootloader file is used. Using the
amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin.

Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20 00:20:07 +00:00
Raul E Rangel 28d4275622 soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices
The PCI interrupt devices were only partially implemented.
* Lacked support for _DIS to disable the bus. Something the kernel does
  while booting.
* Lacked support for APIC vs PIC. This means the devices can only be
used when using the PIC. By looking at the PMOD variable we can handle
both PIC and APIC. This means we can stop hard coding the PCI interrupt
numbers in the ACPI tables.
* I removed INT[E-H] since they are not used.

BUG=b:139429446, b:147042464
BRANCH=none
TEST=Boot with both the APIC and PIC and saw that the link devices work
as expected:
PIC MODE:
[    1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[    2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[    2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15)
[    2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15)
[   13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6
[   13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15
[   27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6
[   27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14

APIC MODE:
[   19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23)
[   19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23)
[   19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23)
[   19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23)
[   34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23
[   34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22
[   66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21
[   66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20

Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-20 00:16:53 +00:00
Raul E Rangel 839f668d89 soc/amd/picasso/acpi: Move _PIC method to root namespace
The _PIC method sets the interrupt model (PIC or APIC). It needs to be
defined at the root level for the kernel to find it. Previously this
method was never getting called, so we were always stuck in APIC mode.

BUG=b:139429446, b:147042464
BRANCH=none
TEST=Saw the method getting called
[    1.251774] ACPI Debug:  "PIC MODE: 0000000000000001"

Change-Id: Idd5e9646df8d56e7cbec2be8b4016c36d81e5fb8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095682
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-20 00:08:21 +00:00
Felix Held f36c38355b soc/amd/picasso/soc_util: use socket type detection
Remove the Kconfig options for per board socket type selection and use
the runtime detection instead.

Change-Id: I82cf922661c24e2a529fa4927893727b643660e3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41518
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 00:06:51 +00:00
Felix Held bf21308705 soc/amd/picasso/soc_util: add socket type detection and printing
Change-Id: I643a4c5f8a42a5fb0603a1a049545b57d16493a6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41517
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 00:06:34 +00:00
Duncan Laurie 4480dc1ca1 device: Add definitions for SoundWire specification
This header implements structures to describe the properties defined in
the SoundWire Discovery and Configuration Specification Version 1.0.

By itself this just provides the property definitions, it is then used
by the code that generates ACPI device properties and by the controller
and codec drivers.

A new header for MIPI vendor/device IDs is also added, with the MIPI
Alliance board members added by default.  This will be used in the same
way as pci_ids.h to track devices added to coreboot.

BUG=b:146482091

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ie9901d26d1efe68edad7c049c98a976c4e4f06f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-19 17:43:11 +00:00
Felix Held 86abc8dff0 soc/amd/picasso/romstage: removed unused include
Change-Id: I550599ae5ef9875ce820a4534d21439ff2027585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-19 16:40:43 +00:00
Keith Hui 5f0e8d8462 superio/winbond/w83977tf: Fix iasl warning
The common PnP serial port DSDT code is intentionally included twice for
two serial ports with different LDNs. Undefine LDN and the PM register
name before redefining for second serial port so iasl doesn't complain.

Change-Id: I031905479c66698fb01da028e3f37d923396d2d9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41095
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-19 08:06:08 +00:00
Angel Pons 14ea2fc90c nb/intel/sandybridge: Do not hardcode resource indices
Other northbridges use an index variable to assign monotonically
incrementing values to each resource. Do it here as well.

Change-Id: I8719a1a5973a10531cf11b3307652212cb3d4895
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-19 07:58:43 +00:00
harshit aae1633069 security/tpm/tspi: Fix handling of white space delimited list
The current implementation uses strcmp() without splitting the list
and therefore returns false even when the string pointed to by
'name' is a part of 'whitelist'. The patch fixes this problem.
Also, update help text of CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA to
space delimited list to align it with the other lists we use.

Change-Id: Ifd285162ea6e562a5bb18325a1b767ac2e4276f3
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-05-19 07:57:23 +00:00
Angel Pons fb6606b8db nb/intel/sandybridge: Correct IOSAV register notes
The IOSAV register descriptions are plagued with errors and nonsense.
Using `git blame` to find the culprit... Zoinks! Turns out it was me!

Rewrite the comment so that the difference between a sub-sequence and a
command is clear. Also, expand the descriptions that could be ambiguous
and fix some insane blunders. CKE and ODT fields are per DIMM and rank!
As per review comments, also invert the order of bitfield value ranges.

Change-Id: Ie384304c565f962fe58baa231c15109eb3d284aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-19 07:56:39 +00:00
Julius Werner 2540037406 tests: Add region-test for rdev API
This patch adds a basic test for the common region and region_device
APIs, sanity checking the basic functions and things like
overflow-handling. There is certainly more that could be added here, but
it's a start.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4932402f54768557e5b22b16e66220bd90ddebfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jan Dabros
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-19 03:22:04 +00:00
Julius Werner 21744811bb tests: Add <tests/test.h> wrapper header and fix --gc-sections
<cmocka.h> requires a few standard headers to be explicitly included
before itself or it will throw compilation errors. Having to always
include these headers in the right order in every test is cumbersome.
Instead, this patch encapsulates the problem in a new <tests/test.h>
header that all tests should include (instead of <cmocka.h> directly).

Also fix --gc-sections in the test framework which needs to be passed
for linking, not for compiling.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4284d74c8673708e21a5266eb42f7b9ae19a1b12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-05-19 03:21:44 +00:00
Chris Wang ed03371e76 soc/amd/picasso: add telemetry setting
Add telemetry setting for SDLE testing

BUG=b:147570294
TEST=Build Morphius and check the setting was been applied

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851
Reviewed-on: https://chromium-review.googlesource.com/2056885
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 19:28:08 +00:00
Felix Held 15fd30f040 soc/amd/picasso/romstage: add missing types.h include
Change-Id: I26f15e7bd2f65e94ed1c2771bd8504114bfcda48
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-18 15:11:22 +00:00
Elyes HAOUAS b74f45e9c4 src: Remove unused 'include <string.h>'
Unused includes found using following commande:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<'

Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18 07:41:24 +00:00
Bill XIE f769ee3e1b mb/lenovo/{x230, t430s}: add H8_HAS_PRIMARY_FN_KEYS for {x230s, t431s}
X230s and T431s have keyboard similar to the one found on t440p, so
H8_HAS_PRIMARY_FN_KEYS and related cmos options may apply to them.

Tested on both X230s and T431s.

Change-Id: I234820b92093acdd64ff60cae39015547b6e981e
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41403
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:41:07 +00:00
Raul E Rangel cbaa835f21 soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs
BUG=b:147042464
TEST=Boot trembyle to OS

Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:40:51 +00:00
Rob Barnes f836a234e2 util/apcb: Add apcb_edit tool
On the Picasso architecture, the PSP is responsible for setting up DRAM
before releasing the x86. The APCB (AGESA PSP Configuration Block)
contains multiple SPDs and the GPIO numbers used to select the correct
SPD. Since the source to build the APCBs is not public, it can't be
built as part of the coreboot build. To work around this problem, we use
a template APCB and inject the relevant information.

BUG=b:147042464

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18 07:40:47 +00:00
Elyes HAOUAS 5dd76fd4cc src: Remove unused 'include <lib.h>'
Change-Id: Iad5540e791075270453a136a058823c28647f93a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18 07:39:17 +00:00
Elyes HAOUAS 82fb12ccec mb/google/{parrot,stout}: Remove unused 'include <elog.h>'
Change-Id: I7c6f47f03f1c83658f4364f81f6436d7b2f4f377
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:38:54 +00:00
Bill XIE 02043c995b 3rdparty/libgfxinit: Update submodule pointer, again
6b95507ec5 has mistakenly reverted
the submodule pointer of 3rdparty/libgfxinit to cdbfce27, canceling
c844d14ca5.

This commit sets it back, recovering c844d14c.

Change-Id: Ib594e40a39ea83dd2238becb287f2516e7c54046
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41400
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:37:09 +00:00
Yu-Ping Wu cabcfe276c libpayload: Fix definitions of minimum integer values
Fix incorrectly defined constants INT16_MIN, INT32_MIN and INT64_MIN,
which recursively call themselves.

BRANCH=none
BUG=none
TEST=emerge-nami libpayload

Change-Id: I1fa8402d318393de2e02f1e632ab78b6ec0768e8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41391
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:34:55 +00:00
John Zhao 7a05e6e2ad soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.

BUG=🅱️146624360
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-05-18 07:34:08 +00:00
Srinidhi N Kaushik d7b9e363e3 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163
Update FSP headers for Tiger Lake platform generated based FSP
version 3163, which includes below additional UPDs:

FSPM:
TcssDma0En
TcssDma1En
FSPS:
PchFivrExtV1p05RailEnabledStates
PchFivrExtV1p05RailSupportedVoltageStates
PchFivrExtVnnRailEnabledStates
PchFivrExtVnnRailSupportedVoltageStates
PchFivrExtVnnRailSxVoltage
PchFivrExtV1p05RailIccMaximum
CstateLatencyControl5TimeUnit
VmdEnable

BUG=none
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icc893073629df59aef60162bed126d1f4b936e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41377
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:33:51 +00:00
Philipp Bartsch 7f5f9331d1 util/cbfstool: fix buffer over-read
Fix unterminated array.

When looking for a type not specified in filetypes (cbfs.h:204), the
loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer
over-read.

Found-by: AFL++ 2.64d rev 1317433
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:32:16 +00:00
Raul E Rangel f39dab1b95 soc/amd/picasso: Switch to using amd_blobs
BUG=b:147042464
TEST=build trembyle and boot to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie6ac8b0701ac27733dd9724873664f5f17fcfa29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18 07:31:35 +00:00
Felix Held 68975b15cf soc/amd/picasso: only link soc_util in ramstage
No code that was or will be upstreamed uses functionality from soc_util
in romstage, so only compile and link it for ramstage.
This also allows to fix the SoC type detection in a follow-up patch
using information that FPS-M will be providing in a HOB.

BUG=b:153779573

Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-18 07:30:59 +00:00
Tim Wawrzynczak 979e80dc47 device/pci_device: Remove useless pci_bus_ops_pci
The struct (formerly assigned to default_pci_ops_bus.ops_pci) only
contained a NULL (well, 0) pointer for the set_subsystem callback, but
usage of that callback is guarded with NULL checks when it is used,
therefore it can be removed.

TEST=still compiles

Change-Id: I3943c8ae73b95e744a317264d7ceb8929cb28341
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41432
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:18:00 +00:00
Sumeet R Pawnikar fa42d568a0 broadwell: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Broadwell SoC based platforms.

BRANCH=None
BUG=None
TEST=Build for broadwell based platform

Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18 07:17:36 +00:00
Elyes HAOUAS 71a9a7c70f mb/portwell/m107: Remove direct 'include <soc/gpio.h>'
Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.

Change-Id: I78f1e250570f1b395c61115d4a872b24b3d58f69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18 07:16:44 +00:00
Elyes HAOUAS 1fb15b0ac5 mb/facebook/fbg1701: Remove direct 'include <soc/gpio.h>'
Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.

Change-Id: Id2663398b9f069ab1f60d63016ea7aa080f66d20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18 07:16:31 +00:00