Commit Graph

35131 Commits

Author SHA1 Message Date
John Su 8eaa5dc684 mb/google/hatch: Add Mushu variant specific DPTF parameters
The change applies the DPTF parameters received from thermal team.

1. Set PL1 Max to 25W
2. Set PL2 Max to 44W
3. Update Temp sensor parameters

BUG=b:152011093
BRANCH=none
TEST=build and verified by thermal team

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I225897832b02f9de6221053b68fbdba30f8b199a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41165
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:16:15 +00:00
Krishna Prasad Bhat ed34967303 soc/intel/jasperlake: Add function to display ME firmware status info
Add function to display ME Host Firmware Status registers. Make use of
print_me_fw_version() from CSE lib to print ME firmware version information.

Add manufacturing mode field in HFSTS1 register for JSL in place of,
spi_protection_mode in TGL.

BUG=None
BRANCH=None
TEST=Build and boot jslrvp. In coreboot logs, ME info can be seen.
ME: Version: 13.5.0.7049
ME: HFSTS1                  : 0x90006255
ME: HFSTS2                  : 0x82100136
ME: HFSTS3                  : 0x00000020
ME: HFSTS4                  : 0x00004800
ME: HFSTS5                  : 0x00000000
ME: HFSTS6                  : 0x00400006
ME: Manufacturing Mode      : YES
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : YES
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: D0i3 Support            : YES
ME: Low Power State Enabled : NO
ME: CPU Replaced            : YES
ME: CPU Replacement Valid   : YES
ME: Current Working State   : 5
ME: Current Operation State : 1
ME: Current Operation Mode  : 0
ME: Error Code              : 6
ME: CPU Debug Disabled      : YES
ME: TXT Support             : NO

Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-18 07:15:59 +00:00
Eric Lai 2abe9cf2d7 mb/google/deltaur: Remove DSP setting
Deltaur does not use DSP so remove the DSP setting.

BUG=b:155360937
TEST=Recording and playing are working fine in OS.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I01c076806448fc73980ec02e7558ccf082723d92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18 07:15:30 +00:00
Eric Lai 7ff5f28228 mb/google/deltaur: Add audio verb table
Add audio verb table provided by vendor.

BUG=b:156447983
TEST=Have beep sound when run "devbeep" in CLI.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I807d84de1677459ea027e645488f485b0ac7b2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41401
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:15:21 +00:00
Eric Lai 4d4424658f mb/google/deltaur: Update audio setting
Deltaur uses HDA codec so we need to set iDisplay Audio Codec
disconnection and enable HdaAudioLink, otherwise the HDA codec won't
respond to commands to execute HDA verbs.

BUG=b:156447983
TEST=No timeout error when run "devbeep" in CLI.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I15d2895866abcf68963c9732ed5d05f32096fc92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41397
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:15:12 +00:00
Eric Lai 54b706e654 soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override
This is a missing config override in fspm_upd.

iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.

BUG=b:156447983
TEST=None

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbbc22d14e06713009c550cbe8a7292de64e1fdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41394
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:14:53 +00:00
Marco Chen e88f0311be mb/google/dedede: update SPD name based on DRAM characteristic
The index of DRAM_STRAPS indicates to a specific DRAM characteristic
instead of a DRAM part number therefore update the existing DRAM SPD
binary to the naming by DRAM characteristic.

BUG=b:152019429
BRANCH=None
TEST=build the image and verify that coreboot log shows the correct SPD
info

Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-18 07:14:43 +00:00
Sumeet R Pawnikar 97c5464443 skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on nami system

Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18 07:13:23 +00:00
Elyes HAOUAS 19c2ce7639 Remove new additions of "this file is part of" lines
Change-Id: I96dfa5b531842afcf774dd33c2dfa532b5d329c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-05-18 07:12:03 +00:00
Elyes HAOUAS 0aad0531dc util/autoport/bd82x6x.go: Drop unused includes
Change-Id: Ifc0bf18dedc112e346062e0e0e988ac102991bb8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40826
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:11:47 +00:00
Wim Vervoorn 30e9149c4f soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD read
Reading the SPD using the SMBUS routines takes a long time because each
byte or word is access seperately.

Allow using the i2c read eeprom routines to read the SPD. By doing this
the start address is only sent once per page.

The time required to read a DDR4 SPD is reduced from 200 msec to 50
msec.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: I44e18b8ba72e1b2321f83402a6a055e2be6f940c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-18 07:11:24 +00:00
Wim Vervoorn 544cc83470 mb/facebookmonolith: Update root port settings
Update monolith root port settings to match those of the original BIOS.

MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced
Error reporting are enabled.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-18 07:10:48 +00:00
Paul Ma d0ded16529 soc/mediatek: dsi: adjust hfp_byte and hbp_byte if too small
If panel has too small hfp or hbp, hfp_byte or hbp_byte may become
very small value or negative value. When very small value or
negative value is used, the panel will be scrolling or distorted.
This patch adjusts their values so that they are greater than
the minimum value and keep total of them unchanged.

DSI transfer HBP or HFP, There are some extra packet. ex. packet
header(4byte) and eof(2byte) and (next)hs packet header(4 byte).
the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte)
and (next)hs packet header(4 byte). So the min hfp_byte is 2 when
HFP = 4.

This is equivalent to the Linux kernel DSI change in:
https://chromium-review.googlesource.com/c/chromiumos/third_party/
kernel/+/2186872

BUG=b:144824303
BRANCH=kukui
TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its
     hbp only 6), the panel can display without scrolling or
     distortions.

Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:10:31 +00:00
Sumeet R Pawnikar e8d1bef8cb jasperlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Jasperlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built for jasperlake system

Change-Id: I9b725d041dcb8847f83ec103e58b9571b4c596ac
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18 07:10:13 +00:00
Sumeet R Pawnikar 4fafd41209 soc/intel/common: add processor power limits control support
Add processor power limits control support under common code.

BRANCH=None
BUG=None
TEST=Built and checked this entry on Volteer system,
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/*

Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18 07:09:25 +00:00
Raul E Rangel 5f52c0e91f soc/amd/picasso: Set VERSTAGE_ADDR for picasso
By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This
causes problems in a non-xip environment because when verstage loads
romstage, it overrides it's memory. So pick a different offset for
verstage.

BUG=b:147042464
TEST=Boot verstage on trembyle and see OS boot.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:09:02 +00:00
Raul E Rangel 8f694dd51f arch/x86/early_ram.ld: Add vboot work buffer
This is required to enable VBOOT_STARTS_IN_BOOTBLOCK and
VBOOT_SEPARATE_VERSTAGE for picasso.

BUG=b:147042464
TEST=Boot verstage on picasso

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3e261a6919a78760d567be9cc684494a5aeab6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-18 07:08:53 +00:00
Shaunak Saha 022d935919 mb/ripto: Update ALC5682 headset interrupt configurations
As per schematics configure headset interrupt as
edge both for ripto and volteer baseboard.

BUG=b:147085988
BRANCH=none
TEST=Build and boot ripto board. Test that jack functionality
is working fine and also confirm with evtest.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I8e1625140ccf55db8cb0fe3c039f1c31c01069b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-05-18 07:07:54 +00:00
John Zhao 9e9f301b58 soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method
CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW
method. Change the operation region from SystemIO to SystemMemory to
resolve this execution failure.

BUG=b:140290596
TEST=Built and booted to kernel. _DSW method executes successfully without
ACPI AE_LIMIT error.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-18 07:07:03 +00:00
Patrick Georgi 81a30ec3a7 util/release: Check that HEAD isn't used as reference
genrelnotes moves the tree between commits and so a relative location
like HEAD isn't stable. Since I ran into the HEAD issue while preparing
for two consecutive releases, let's guard against it.

Change-Id: I70c6812cdfe0d0671b3d653744a062d9920a2394
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:06:42 +00:00
Patrick Georgi d906b21e2e util/release: Improve reporting of required tools
genrelnotes checks for cloc, git and rename but only reported about
needing the first two, so mention `rename` in missing message.

Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:06:22 +00:00
Patrick Georgi 33e19ac619 Documentation: Fix 4.12 release notes, improve checklist
Since I seem to forget to remove "Upcoming" in the release notes
every single time, and others might as well, fix it here and also
tell future release managers to take care of that.

Change-Id: I8ffe34f25e954621bdd635e115a8b1a914df9c27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:04:04 +00:00
Angel Pons 6aa7cca815 nb/intel/sandybridge: Use or-based logic for RANKSEL
NO_RANKSEL was introduced because it appeared less often and it did not
cause any lines to become too long. To simplify macro transmutation, add
the RANKSEL opposite and keep NO_RANKSEL as a no-op to ease replacement.

Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: I5d7aad59fc79840da7de2e9421b84834a6024eb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40977
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:03:44 +00:00
Angel Pons ca00dec624 nb/intel/sandybridge: Program IOSAV with macros
This is a temporary solution to simplify refactoring verification.
Programming a subsequence involves writing a group of four registers.
Abstract this into a "program subsequence" operation. This eliminates
register write noise, which should improve the readability of the code.
To replace the register writes with assignments to struct fields, we
would need to have the values as parameters of a single macro. So,
unroll SUBSEQ_CTRL and SP_CMD_ADDR into parameters of IOSAV_SUBSEQUENCE.

Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: I23f7706ba8a87c1c26f9d40a50b6d47dcf95106a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-18 07:03:22 +00:00
Angel Pons 8e66124240 nb/intel/sandybridge: Add and use BROADCAST_CH for IOSAV
We have a single IOSAV sequence that is broadcast across all channels.
Introduce the BROADCAST_CH macro, so that we can use the per-channel
register definitions. Treating all IOSAV sequence writes the same eases
the refactoring done in subsequent commits. Also, drop the broadcast
register definitions for the IOSAV commands, as they are now obsolete.

Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: I2dbb100fcad68d128e92b1bc9321fc1e53b748c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40976
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:03:02 +00:00
Elyes HAOUAS d13bd05b7a nb/intel: Const'ify pci_devfn_t devices
Change-Id: Ib470523200929868280f57bb0cc82b038d2fedf6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:02:05 +00:00
Elyes HAOUAS 2b79203bdb x86/include/arch/mmio.h: Convert to 96 characters line length
Change-Id: I93d0ef6db417904c345fe7b76730bcb70ba25089
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41361
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:01:41 +00:00
Elyes HAOUAS b3162b5a38 mainboard/*/*/*.cb: Remove leading blank lines from SPDX header
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18 07:01:11 +00:00
Elyes HAOUAS 44e310bc6c mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX header
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:00:58 +00:00
Elyes HAOUAS c4b70276ed src: Remove leading blank lines from SPDX header
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:00:27 +00:00
Seunghwan Kim 189e753cbf driver/i2c/max98390: Correct included file path
Fix coreboot build error with adding this driver

BUG=b:149443429
BRANCH=None
TEST=built without errors

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I46bced77a50903c16239a5162d144697e9d704a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 05:53:17 +00:00
Marshall Dawson 3e30c1284f 3rdparty/amd_blobs: Update with Picasso images
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie886815ed354762ea52fd6a76169cf25576f8852
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-17 21:06:52 +00:00
Angel Pons 7449b625f8 sb/intel/lynxpoint/lp_gpio.h: Include stdint.h
The struct definition makes use of types defined in that header.

Change-Id: I1d989298b8bf6266905330491c136874be7f5e28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-17 20:19:16 +00:00
Angel Pons c1c6c51ec0 drivers/xgi: Remove dead code
This was used by the now-gone Asus KFSN4-DRE mainboard. Drop it.

Change-Id: Id00c883ed0f80e7af96fdf3f6e2985dd5b227831
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-17 15:34:17 +00:00
Keith Hui 81f9ae9ff1 mb/asus/p2b: Remove variant validation guards from DSDT
With conversion to variant structure complete, remove temporary guards
inserted to help validate the move.

With this change, all P2B family boards (currently p2b and p2b-ls)
share the same S-state declarations.

TEST=No apparent ACPI regression observed on p2b-ls.

Change-Id: Ibd6e49adeae2a42800ee5bfd74b3850eb19843a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-17 14:19:15 +00:00
Sridhar Siricilla 99dbca381b soc/intel/common: Rename cse_is_hfs3_fw_sku_custom()
Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and
rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU
references to CSE Lite SKU.

TEST=Verified on hatch

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-05-17 08:33:00 +00:00
Furquan Shaikh 17b4803381 soc/intel/common/block/acpi: Mask lower 20 bits of TOLUD
Lower 20bits of TOLUD register include 19 reserved bits and 1 lock
bit. If lock bit is set, then northbridge.asl was reporting the base
address of low MMIO incorrectly i.e. off by 1. This resulted in Linux
kernel complaining that the MMIO window allocated to the device at the
base of low MMIO is incorrect:

pci 0000:00:1c.0: can't claim BAR 8 [mem 0x7fc00000-0x7fcfffff]: no compatible brw
pci 0000:00:1c.0: [mem 0x7fc00000-0x7fcfffff] clipped to [mem 0x7fc00001-0x7fcfff]
pci 0000:00:1c.0:   bridge window [mem 0x7fc00001-0x7fcfffff]

This change masks the lower 20 bits of TOLUD register when exposing it
in the ACPI tables to ensure that the base address of low MMIO region
is reported correctly.

TEST=Verified that kernel dmesg no longer complains about the BAR at
base of low MMIO.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4849367d5fa03d70c50dc97c7e84454a65d1887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41455
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-17 04:07:16 +00:00
Furquan Shaikh edf2c8eb55 soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax
This change updates northbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-17 04:06:03 +00:00
Furquan Shaikh 6186cbcdc7 Revert "device: Enable resource allocator to use multiple ranges"
This reverts commit 3b02006afe.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

BUG=b:149186922

Change-Id: Id9872b90482319748b4f3ba2e0de2185d5c50667
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41413
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:48:52 +00:00
Furquan Shaikh bca71f643c Revert "device: Enable resource allocation above 4G boundary"
This reverts commit 44ae0eacb8.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

BUG=b:149186922

Change-Id: I90f3eac2d23b5f59ab356ae48ed94d14c7405774
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:48:11 +00:00
Furquan Shaikh 196d8559d9 Revert "pciexp_device: Add option to allocate prefetch memory above 4G boundary"
This reverts commit dcbf6454b6.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

Change-Id: I58c9fff1a18ea1c9941e29c2c6e60e338c517c30
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-16 17:48:04 +00:00
Furquan Shaikh 563424e986 Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports"
This reverts commit 2412924bc7.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

BUG=b:149186922

Change-Id: Iea6db8cc0cb5a0e81d176ed3199c91dcd02d1859
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:47:57 +00:00
Michał Żygowski 72f06ca554 mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support
Based on the autoport. The OptiPlex 9010 comes in four different sizes:
MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly
different, but they are designed with intercompatibility in mind. With
small devicetree overrides it should work on OptiPlex 7010 and other
OptiPlex 9010 variants as well.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:38:46 +00:00
Michał Żygowski fba08308f0 superio/smsc/sch5545: add support for SMSC SCH5545
The SMSC SCH5545 is very similar to the publicly available
datasheet for the SCH5627.

TEST=use PS2 keyboard and mouse, serial port, runtime registers and
Embedded Memory Interface on Dell Optiplex 9010

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If8a60d5802675f09b08014ed583d2d8afa29fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40350
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:37:29 +00:00
Raul E Rangel 6191b85f87 drivers/i2c/designware: Check if the device is powered
If the device doesn't return a valid component type, that means the
device is non-functional.

The dw_i2c_regs had invalid offsets for the version field. I got the
correct value from the DesignWare DW_apb_i2c Databook v2.02a. It also
matches what the Picasso PPR says.

I also print out the version field of the controller.

BUG=b:153001807
BRANCH=none
TEST=Tested on PSP where I2C is non functional. Also tested on trembyle
and verified i2c was initialized.
Saw the following in the logs
I2C bus 2 version 0x3132322a

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5527972508e0f4b35cc9ecdb1491b1ce85ff3af
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144540
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40870
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15 17:32:47 +00:00
Sridhar Siricilla 6ad7010542 soc/intel: Correct comment on HMRFPO_ENABLE HECI command
Correct comment on HMRFPO_ENABLE flow for CSE Lite SKU. In order to place
CSE into SECOVER_MEI_MSG mode, below procedure has to be followed.
1. Ensure CSE boots from RO(BP1).
	- Set CSE's next boot partition to RO
	- Issue GLOBAL_RESET HECI command to reset the system
2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required.

TEST=Verified on hatch

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I213e02ba3898194fa6c8fe38fab34b5c19f25aa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41340
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15 07:33:50 +00:00
Alex Levin 9e8dd06cd4 mb/google/volteer: Add delay to WWAN GPIO init sequence
Based on Fibocom HW user manual RESET should be deasserted at least 20ms after the power on pin.
The design for the reset pin is open drain connected to a pull up, so it is set to high-Z (configured as GPIO in) after 20ms.

BUG=b:152013143
BRANCH=none
TEST=traced the signals using a scope to verify timing is met.

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I7c947d1bc4cce1f97383a2f2c254986e182661c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15 04:32:41 +00:00
Rajat Jain ecc4c4e5f1 acpigen_ps2_keybd: Add keymap for Power key
Power key is a special non-matrixed key. Chrome /powerd
only listens to the keyboard device for this key, so add
its keymap.

BUG=b:155941390
TEST=Test that power key generates KEY_POWER in linux evtest

Change-Id: I570602d9febcb5c17e58761f2004ee88be16c27f
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-15 03:52:39 +00:00
Shaik Sajida Bhanu 9a41af60c4 trogdor: Update pull for Sd-card detect pin
Configuring pull for SD-card detect pin.
Without this SD-card detection is not working as expected

Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Change-Id: I77bf355a049224784a160defa6bee66d0f9ceb75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-14 23:29:42 +00:00
vsujithk e8ee6f975b sc7180: GPIO: Add I2S configuration for sc7180
Configuring GPIO Pins as I2S mode for Audio speaker.

Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0
Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-14 23:29:06 +00:00