Commit Graph

43263 Commits

Author SHA1 Message Date
Jason Glenesk 8d35428331 soc/amd/cezanne: Generate IVRS for cezanne
Generate IVRS for cezanne using common IVRS generation code.

BUG=b:190515051
TEST=Build cezanne coreboot image. Compare IVRS table with agesa
generated tables.

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05 15:54:50 +00:00
Jason Glenesk f934fae032 soc/amd/picasso: Move IVRS generation code to common
Move IVRS acpi table generation code to common, so that it can be shared
by other programs.

BUG=b:190515051
TEST=Build picasso coreboot image. Compare IVRS tables before/after
change.

Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-05 15:54:47 +00:00
Raymond Chung 3fc0190bbc mb/google/dedede: Create bugzzy variant
Create the bugzzy variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:192521391
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BUGZZY

Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 15:46:12 +00:00
Casper Chang 946d73490a mb/google/brya/variants/primus: enable PS2 interface
BUG=b:187969783

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1e063524cfa4121c38cfed23e95557953511d884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-05 15:45:12 +00:00
Patrick Georgi 4b8b2a0f0b util/kconfig: Provide default for DEFCONFIG
Our documentation claims that the DEFCONFIG make variable, used for
targets such as savedefconfig, defaults to 'defconfig'.
With the update to kconfig 5.13 we lost this default, so bring it back.

Fixes: 53ea1d44f0 ("util/kconfig: Uprev to Linux 5.13's kconfig")
Resolves: https://ticket.coreboot.org/issues/317
Change-Id: Idb88b69ffa855fa97df8c821601308e717575550
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56718
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05 02:48:56 +00:00
Julius Werner 763db46ccd MAINTAINERS: Update vboot maintainers
Add current maintainers for vboot-related code, and combine the vboot
and vboot2 sections which are not really separate anymore. What's left
in vendorcode/google/chromeos isn't really related to vboot anymore
since the vboot code was moved under src/security, so take it out of
there.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I59a2df9c1580291a6d29537868aab0e1b339a2ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-04 19:46:18 +00:00
Scott Chao f2be7d6056 mb/google/brya/variants/gimble: Remove DPTF fan control
BUG=b:195378817
BRANCH=none
TEST=Check fan is able to control by EC

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I84c020e470194072bb796f75f8a1304832504469
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56768
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:55:55 +00:00
Ren Kuo 163dfe68f6 mb/google/dedede/var/magolor: Modify SSFC for camera and touchscreen
The all shipped magolor and maglia has SSFC= 0x840.
The value is defined as 5M MIPI camera.But the value:0x840 will
conflict with the updated touchscreen field.
It will cause some touchscreen no function if make auto-update new
firmware.The CL would correct the field error.

The original fields:
CAMERA_WFC 38 40
TS_SOURCE  41 44

Correct fields:
MIPI Cam
  CAMERA_WFC 38 40
  CAMERA_UFC 41 42
  CAMERA_VCM 43 44
Touch-screen
  TS_SOURCE  45 48

The SSFC value of Magolor:
CAMERA_OVTI5675  5M AF (SSFC = 0x840)
CAMERA_OVTI8856  8M AF (SSFC = 0x880)

BUG=b:194639170
TEST=Build firmware and verify on camera and touch-screen devices

Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56685
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:16:09 +00:00
Aamir Bohra 9fe70ed197 mb/amd/bilby: Add support for HDMI display
DDI 0/1 ports are shared for DP and HDMI. This implementation
adds support for HDMI display when HDMI is set as connector type
in ddi descriptors.

TEST=verify display over HDMI(0 and 1) in OS.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: I9697211c556f12d1fc0d49418b227fbe6b342673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04 15:16:05 +00:00
Paul Menzel 9e34060d52 acpi/acpigen_ps2_keyb: Align comments using tabs
Fixes: ffd80fd2 ("arch/x86/acpi: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLE")
Change-Id: I2cca8cdbbd3607acca88da7b273ca6b080db9e7c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:16:02 +00:00
Mark Hsieh f41da47d34 mb/google/brya/variants/gimble: Update overridetree for gimble
According to the schematic diagram of proto, added drivers/i2c/max98390 to device ref i2c0 and deleted device ref hda.

BUG=b:191811888
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I0f0a8c84db3fbc963797d11246c5d31b395bb744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:15:59 +00:00
Ricardo Quesada d45e70c124 Move elog_internal.h to commonlib/bsd/include
Move elog_internal.h to commonlib/bsd/include/bsd/.
And rename it from elog_internal.h to elog.h.

Since this file will be included from util/ it also converts the "uNN"
types into "uintNN_t" types.

The two defines that are not used by util/ are moved to
drivers/elog/elog.c, the only file that includes them.

Move also the function elog_verify_header() from drivers/elog/, to
commonlib/bsd/elog.c since this function will be called from util/
as well.

The rationale behind moving elog's defines & structs to
commonlib/bsd/include is to make them available to util/ tools and/or
payloads (should it be needed in the future).

The files that are being relicensed to BSD were coded by Duncan Laurie,
and he is Ok with the relicense.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04 15:15:55 +00:00
Ricardo Quesada 470ca5714f Move post_codes.h to commonlib/console/
Move post_codes.h from include/console to
commonlib/include/commonlib/console.

This is because post_codes.h is needed by code from util/
(util/ code in different commit).

Also, it sorts the #include statements in the files that were
modified.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:15:51 +00:00
Aamir Bohra 1b9ae18726 mb/amd/bilby: Enable DP2 and DP3 enumeration
DP2 and DP2 is muxed with USBC port. This implementation
configures mux for DP functioanlity.

TEST=Verify display over DP2 and DP3.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: If0c8dfbb47175789bb27d4506c1e8b45c425c76a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-04 15:15:48 +00:00
Nico Huber 12441dce06 console/hw-debug_sink: Update for fast/slow console distinction
Change-Id: I9ac110c7b812f912f0f87cbe4aa218d4a78e6aaf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:45 +00:00
Nico Huber 234e7ecb29 soc/intel/cannonlake: Allow to configure maximum package C state
Sometimes it's preferable or even necessary (e.g. stability issues) to
limit the maximum package C state. Let's add a devicetree option that
keeps the current behavior if it is left unset.

Change-Id: I0dc254d34f46de4c65cb85cc92e4b7f26618888d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:42 +00:00
Nico Huber e4bc55b843 soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is given
Change-Id: I4f9b62fd944d8a91d53bc584c88797f23de1e5ca
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-04 15:15:39 +00:00
Nico Huber 6ac8a9f826 soc/intel/cannonlake/vr_config: Print configured values
These values are quite important and our default tables sometimes have
holes. We should at least make it visible what the resulting settings
are.

Change-Id: Ic716d073da1c2638c4b16f2eac01b83a0768d22f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:35 +00:00
Nico Huber b06d847ea9 soc/intel/cannonlake/vr_config: Add TDC values for CFL-H 6+2
Values were taken from PDG (571391), 51.3 IMVP8 Voltage and Current
Requirements.

Change-Id: Iffa29386cb7da333353dafd0ba3a61ca61a0ccac
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-04 15:15:32 +00:00
Nina Wu c25aa5b47e soc/mediatek/mt8195: Add devapc basic drivers
Add basic devapc (device access permission control) drivers.

DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.

1. Initialize devapc.
2. Set master domain and secure side band.
3. Set domain remap.
4. Set default permission.

Change-Id: I3677657a117caed0d73526f78b0ebe8180148335
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-04 09:23:45 +00:00
Shelley Chen 530624de21 3rdparty/qc_blobs: Uprev to new HEAD (98db386)
Now that gsi_fw blob has landed, need to uprev the qc_blobs.

Change-Id: I0bf67a560ee2e5d771bdb71b60e3d3d372dad567
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56776
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 23:40:01 +00:00
Thejaswani Putta 8239d076bf mb/google/brya: Add RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 6 and provide the reset GPIO / src clk pins.

BUG=None
BRANCH=None
TEST=Build and boot the coreboot image, check if device is enumerated
in the lspci list after warm/cold reboot cycles, run suspend cycles and
check if WWAN is entering L2 LPM.

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-03 21:47:05 +00:00
Vinod Polimera e8cd480046 sc7180: Add display support for mipi panels
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels.
- add simple rm69299 panel as an example to append new mipi panels.
- use existing edid struct to update mipi panel parameters.
- add dsi command tx interface for mipi panel on commands.

Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 21:22:26 +00:00
Scott Chao 8ca68cf2ae mb/google/brya/variants/primus: configure correct type-c port
BUG=b:195274799
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I4abf7b2d98b188735ef79f8ffbee4c02099ec021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56583
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 20:50:45 +00:00
Sean Rhodes bc35bed18e soc/intel/*: Allow configuring 8254 timer via CMOS
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-03 15:21:04 +00:00
Zhuohao Lee c0308eb860 mb/google/brya: Introduce new baseboard brask
This patch initiates the brask setting which includes
the gpio and device tree setting.

BUG=b:191472401
BRANCH=None
TEST=build pass

Change-Id: I1bb42c7bb2492402de0810bc4ab2e8d8c0e2392b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-03 15:19:40 +00:00
Dtrain Hsu c7fd6f2f47 Revert "mb/google/dedede/var/cret: Disable SDCard controller"
This reverts commit f294378622.

Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.

BUG=b:194961854
TEST=Build and boot to OS.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I929369c9419375e74be61a4ff3e5566b0f41ce65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-03 15:19:09 +00:00
MAULIK V VAGHELA 8326fc0164 mb/google/brya: Disable crashlog on brya
Crashlog is a debug feature and not used in normal mode of operation.
Disabling this feature will allow us to disable unused IPs and also
provide boot time savings of ~5-7 ms.

BUG=b:195327879
BRANCH=None
TEST=Platform boots and no function impact

Change-Id: I1f7def4ea41ff7a566aada080be1e791c11766e6
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56654
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 14:50:13 +00:00
Ian Feng 583a54654a mb/google/brya: Create felwinter variant
Create the felwinter variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:194431541
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_FELWINTER

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Iff2b9daec40995a013f9fe0dd76ad667d1807d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56765
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03 13:54:53 +00:00
Wisley Chen 5d74ccf1c3 mb/google/brya/variants/redrix: Init devicetree for redrix
Init basic override devicetree based on schematics

BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage

Change-Id: I9fb752fe8280893b84c172d8a519578fa4220184
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-02 17:37:31 +00:00
Scott Chao 37d14cfd30 mb/google/brya/variants/gimble: configure correct type-c port
Change TypeC port1 usb3 port="3".

BUG=b:194472269
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Iaba27aad2adfb0a9e83058ac756ca46a762107bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56545
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 17:37:20 +00:00
Angel Pons 35041339dc soc/intel/broadwell: Drop early BAR macros
They are used at most once. Use the actual values and drop the macros.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I9c1c3ebbbfa64a5eeea3bd5551c3d0068ac0dab2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55799
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:53:46 +00:00
Angel Pons b5d56f9118 soc/intel/broadwell: Replace soc/intel/common include
Broadwell now uses the Lynx Point hda_verb.c and should thus use the
corresponding header as well.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I9b8ca91bed67be9c6850bd51f4c81e002a0f5aef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55797
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:53:08 +00:00
Angel Pons 024e0afa8f soc/intel/broadwell/pch/pch.c: Drop unused include
For some reason, this change makes ramstage slightly smaller.

Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55583
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:43:06 +00:00
Angel Pons d0ef3a46d9 soc/intel/broadwell: Drop unused function declarations
These functions are never defined. Remove the unused declarations.

Change-Id: I4204265680d06bf83fc42f061fd7270ff8e3305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55798
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:29:26 +00:00
Angel Pons 12fc21b1cf soc/intel/broadwell: Rename `ramstage.h`
This file only contains the `broadwell_run_reference_code()` function
prototype (either a declaration or an inline stub definition). Rename
this file to refcode.h and only include it where necessary.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55582
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:29:10 +00:00
Matt DeVillier 94aa18f527 payloads/tianocore: update MrChromebox UEFIPAYLOAD branch
Update tianocore branch used with default UEFIPAYLOAD option to
mrchromebox/uefipayload_202107 (July 2021) branch. This branch is
rebased on edk2 upstream commit 12e34cd2f7900578ee83cb01b8f1696a7bb7511b
[OvmfPkg/Bhyve: clean up TPM_ENABLE remnants] vs tag edk2-stable202105.

The main changes are fixes for e820 table parsing and support to disable
"Above 4G decode", which is required to boot distros with bootloaders
that expect to be loaded into RAM below 4G. This fixes booting with
Qubes, ZorinOS, Proxmox, among others.

Additionally, several commits on top of upstream have been consolidated,
reworked, and/or reordered for readability and maintainability.

Change-Id: I6f04fd027a0599ca6892a1376938108a2e402ac2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-02 15:19:41 +00:00
Werner Zeh 78ec750610 mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed
Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.

For now, the PCI devices with the ID 110a:403e and 110a:403f needs this
master bit to be set.

Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:08:43 +00:00
Werner Zeh 4cec1a2770 mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scan
Boards based on mc_ehl have, just like some mc_apl variants, legacy
devices on the PCI bus which take longer to boot. In order to ensure
that they will be enumerated correctly wait for them to come up before
PCI scan starts.

TEST=Checked that the new message is visible in the log.

Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:07:23 +00:00
Lucas Chen c1adf40e11 mb/google/kukui: Add new config 'pico' in coreboot
Add new board 'pico' and set correct ram_id offset.

BUG=b:194985056
TEST=None
BRANCH=kukui

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I33c37d99fa0451239bc6626e71bfddb29a11e97b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-08-02 15:07:10 +00:00
Yu-Ping Wu 941db0e55c helpers: Add GENMASK macro
The GENMASK is defined in multiple files (with various names such as
MASKBIT), which sets certain consecutive bits to 1 and leaves the others
to 0. To avoid duplicate macros, add GENMASK macro to helpers.h.

GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For
example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000.

Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in
mmio.h.

BUG=none
TEST=make tests/commonlib/bsd/helpers-test
TEST=emerge-cherry coreboot
BRANCH=none

Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-08-02 15:01:54 +00:00
Varshit B Pandya 5d71994c02 mb/google/brya: Update entries for UFC to support IMX208
1. Replace OV5675 ACPI entries with IMX208
2. Replace FW_CONFIG name
3. Add support for NVM inside UFC

BUG=b:190674542
TEST=Build and boot to OS on Brya, raw capture on UFC

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-02 15:01:26 +00:00
Varshit B Pandya 7a8c68ad97 mb/google/brya: Configure H21 as GPO and A17 as low
As per the schematics, UFC has on card oscillator so we donot need
H21 in NF1 that is IMGCLKOUT
H21 is used to enable this oscialltor so configuring it as 1

A17 is configured as high while _ON method is called by driver and
it is  configured as low when _OFF method is called by driver.
Hence coreboot should configure it as low on boot.

BUG=b:190674542

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:01:19 +00:00
Sunwei Li a23d0b6634 mb/google/dedede/var/cappy2: Disable external bypass VR
The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable

BUG=b:194146867
BRANCH=dedede
TEST=VCCIN_AUX is disable

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-02 15:01:06 +00:00
Sunwei Li e9211729a4 mb/google/dedede/var/cappy2: Add Tpm2.0 device support
Using Tpm2.0 device instead of the Cr50 in cappy2

BUG=b:191743435
BRANCH=dedede
TEST=tpm2.0 device function is ok

Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 15:00:55 +00:00
Angel Pons 29924b24fa soc/intel/broadwell: Rename `SA_DEV_ROOT`
For consistency with Haswell, rename this macro to `HOST_BRIDGE`.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 14:59:57 +00:00
Angel Pons 6672dff088 soc/intel/broadwell: Drop helper functions
Done for consistency with Haswell in order to ease unification.

Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55527
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 14:59:52 +00:00
Angel Pons 863efe4545 nb/intel/haswell: Move MRC glue code into a subfolder
Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future
commits will move the Broadwell MRC/refcode glue code to be in Haswell
northbridge scope, so plan in advance.

Tested on Asrock B85M Pro4, still boots.

Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 14:59:45 +00:00
Angel Pons bc04997f75 nb/intel/haswell/gma.c: Add ULX PCI device IDs
Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50137
Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02 14:58:56 +00:00
Jason Glenesk fbc46a3bfb soc/amd/common/block/acpi: Add IVRS kconfig
Add new IVRS kconfig option to control IVRS generation.

BUG=b:190515051

Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-31 09:15:37 +00:00