Commit Graph

19221 Commits

Author SHA1 Message Date
Jonathan Neuschäfer 4247426be6 riscv: Use the generic src/lib/bootblock.c
TEST=Compiled for and ran on spike; it booted as before.

Change-Id: Id173643a3571962406f9191db248b206235dca35
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16995
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-15 00:26:28 +02:00
Jonathan Neuschäfer bebeb7497d arch/riscv: Remove unused bootblock_simple.c
Change-Id: Id30463d1809d0a31c9d3825642dce66f3ab2750d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-15 00:25:33 +02:00
Jonathan Neuschäfer e2e40cc17e riscv: Clean up {qemu,spike}_util
spike_util.h:
 - (LOG_)REGBYTES and STORE are already defined in
   arch/riscv/include/bits.h.
 - TOHOST_CMD, FROMHOST_* are helper macros for the deprecated
   Host-Target Interface (HTIF).

qemu_util.c:
 - mcall_query_memory now uses mprv_write_ulong instead of first
   translating the address and then accessing it normally. Thus,
   translate_address isn't used anymore.
 - Several functions used the deprecated HTIF CSRs mtohost/mfromhost.
   They have mostly been replaced by stub implementations.
 - htif_interrupt and testPrint were unused and have been deleted.

spike_util.c:
 - translate_address and testPrint were unused and have been deleted.

After this commit, spike_util.c and qemu_util.c are exactly the same and
can be moved to a common location.

Change-Id: I1789bad8bbab964c3f2f0480de8d97588c68ceaf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16985
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15 00:25:05 +02:00
Jonathan Neuschäfer 2af174a7dc riscv and power8: Convert printk/while(1) to die
Change-Id: I277cc9ae22cd33f2cd9ded808960349d09e8670d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16984
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15 00:24:46 +02:00
Daisuke Nojiri 03bf301d82 vboot: Stop creating backup space in TPM
There is no code which uses the backup space in TPM created for vboot
nvram.

All chromebooks currently supported at the trunk store vboot nvram
in flash directly or as a backup.

BUG=chrome-os-partner:47915
BRANCH=none
TEST=emerge-samus coreboot

Change-Id: I9445dfd822826d668b3bfed8ca50dc9386f2b2b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5cee2d54c96ad7952af2a2c1f773ba09c5248f41
Original-Change-Id: Ied0cec0ed489df3b39f6b9afd3941f804557944f
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/395507
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/16997
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-13 18:22:03 +02:00
Daisuke Nojiri 165af1c5c2 gitconfig: Allow user name and email to be in includes
This patch adds '--includes' option to 'git config --global' command
to allow user name and email to be defined in a file included from
the global gitconfig (~/.gitconfig) file.

BUG=none
BRANCH=none
TEST=make gitconfig with ~/.gitconfig including another file which
defines user.name and email.

Change-Id: I4fe61078b143c3a2e26b0be69c3ca8e6f069d8b0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/16912
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-13 18:21:17 +02:00
Ben Gardner d770bad317 coreinfo: make the CBFS list scrollable
This enables viewing more than ~20 files in the file list on the left.
Arrows are added to indicate that more items are available off-screen.
This mimics what was done in pci_module.

Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14546
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-13 18:21:02 +02:00
Arthur Heymans 1190e9cf42 x60,t60: do not add etc/ps2-keyboard-spinup for non-seabios payloads
Regardless of the payload chosen a file etc/ps2-keyboard-spinup
is added to cbfs. With this fix this file is only added to cbfs when
seabios is choses as a payload.

Change-Id: I37cf4c998856db2d297356776752643dba46a8f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16146
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-13 14:59:16 +02:00
Arthur Heymans 62f4dad88d i945/gma.c: Only init LVDS if it is detected
Some devices have no LVDS output but if no VGA is connected or
no EDID can be found, it will try to init LVDS.

This patch detects the presence of an LVDS panel and makes sure that
LVDS is not initialized when it is absent.

Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16513
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-12 22:57:05 +02:00
Barnali Sarkar 4aa295ca28 src/cpu: Fix location for cpu_microcode_blob.bin in COREBOOT CBFS only
The CPU_MICROCODE_BLOB_CBFS_LOC should only be specified for COREBOOT CBFS,
not for other CBFS.

BUG=none
BRANCH=none
TEST=Built and boot kunimitsu

Change-Id: I58bb289e6c9add2647876ef817b7920f6e7b427a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16932
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11 23:36:18 +02:00
Arthur Heymans fe3eabcaed nb/gm45/gma.c: use linux code to compute LVDS dotclock divisors
This reuses linux code (at least 4.1) to compute the graphic clock
divisors for LVDS displays on the gm45 northbridge.
The divisors m1, m2, n, p1, p2 need to be such that
"BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)
/ (p1 * p2)" is as close as possible to the target_frequency.
On g4x hardware the BASE_FREQUENCY is 96000kHz.

This potentially increases LVDS display compatibility.

Change-Id: I2323af5756431e89769f95059790f5a922af14b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11 23:35:39 +02:00
Arthur Heymans 7141ff3b9f nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size
Change-Id: I2b8c4ef75cca9f9d5251789cda4187a02076b69d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16964
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11 23:35:11 +02:00
Arthur Heymans e1f0ac4baa lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O reads
Requesting low power acpi cpu c-states has two software interfaces:
Using P_LVLx I/O reads or using equivalent MWAIT requests.
This change makes it more consistent with newer targets that use MWAIT
requests.

There also exists extended intel acpi c-states which can be enabled
in two ways:
- using a substate hint to the mwait request (defined in bios);
- setting a model specific register (msr)

Currently this is done by setting the right msr bits but with this
change one can experiment by adding substate hints.

Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14801
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11 23:34:18 +02:00
Elyes HAOUAS 49a7c37de9 southbridge/nvidia: Remove commented code
Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16899
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11 23:33:23 +02:00
Elyes HAOUAS 571fb1fb44 mainboard/apple: Use C89 comments style & remove commented code
Change-Id: I81c32c618627507cc3a83f60f565a73e5e6d7a13
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11 23:33:05 +02:00
Elyes HAOUAS 46829869c8 mainboard/aopen: Use C89 comments style & remove commented code
Change-Id: I0014fc030888d71f7951c97bccc7cef0e1c45186
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11 23:32:53 +02:00
Arthur Heymans 626f8c8440 i945/raminit.c: correctly write CLKCFG for 945GC
MHCBAR(CLKCFG) was previously incorrectly written by the
sdram_program_memory_frequency function which required falsely
limiting the max dram frequency for 945GC.

TESTED on Intel d945gclf (memclock 667 and fsb 533) and
Gigabyte ga-945gcm-s2l (memclock 667 and fsb 1067)

Change-Id: I520efd69fa09fc9fde87c5301fd81121fde6a700
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-10-11 23:32:37 +02:00
Nico Huber 6f8b7df8ab cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE
An epic battle to fix Nehalem finally ended when we found an odd mask
set in SMRR. This was caused by a wrong calculation of TSEG size. It
was assumed that TSEG spans the whole space between TSEG base
and GTT. This is wrong as TSEG base might have been aligned down.

TEST: On X201, copied 1GiB from usb key to sd-card and verified.

Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7
Found-by: Alexander Couzens, Nico Huber
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-11 11:37:10 +02:00
Elyes HAOUAS c9848a82e2 intel/i945: Use "IS_ENABLED" for fsbclk & memclk
Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16958
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-10 22:33:12 +02:00
Patrick Georgi 519c4b7298 util/scripts: add gerrit-rebase script
gerrit-rebase is a gerrit-context aware rebase script. Given a source
and a target branch (that need to have a common ancestor), it prepares
a rebase todo list that applies all commits from source that aren't
already found on target.

It matches commits using Reviewed-on lines in the commit message that
are added by gerrit when submitting commits using the "cherry-pick"
strategy.
This has been shown to be the best preserved meta data to work from in
existing data (Change-Id was mangled in all kinds of ways).

Change-Id: I9618c1b66ebc1fb7ed006efbc1665fb08386e1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16695
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10 20:18:57 +02:00
Arthur Heymans 0de17e74ff gigabyte/ga-g41m-es2l: add VESA mode to Kconfig
This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the
gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and
vesamode in menuconfig.

Change-Id: I84b61118fa0419d49d2498b66029711cdce97576
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16501
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10 18:25:58 +02:00
Arthur Heymans de14ea77c3 x4x/gma.c: Add VESA native resolution mode
This patch implements native resolution, VESA mode, on the VGA output of
x4x.

It relies on EDID to modeset, but has a fallback-mode (640 x 480 @
60Hz) if this is no EDID could be found. This fallback mode only works
in textmode since in VESA mode some payloads (grub2) rely on VBE info,
which is being generated from an EDID.

Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16498
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10 18:25:30 +02:00
Alexander Couzens eff596b51a ifdtool: don't write unused regions into a layout file
flashrom treats them as invalid because start > end.

Change-Id: I1c8b4563094823ebd9b1193b91e7b4a748955228
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16936
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10 18:01:00 +02:00
Elyes HAOUAS 6ed319a796 mainboard/advansus: Use C89 comments style & remove commented code
Change-Id: Ib44bc66e02901dbde14361091a049f71c3ecb840
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16921
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-10 17:13:14 +02:00
Elyes HAOUAS 023e284a06 mainboard/avalue: Use C89 comments style & remove commented code
Change-Id: I416d3c212653260a28cb07ed86fda34b736ba4ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16926
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-10 17:12:59 +02:00
Sathyanarayana Nujella 46445fc3c7 google/reef: update timing of sdmode toggling
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.
sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.

BUG=chrome-os-partner:58356
BRANCH=None
TEST=while audio playback via headset, remove headset.
Audio will be switched playback to speaker. Observe if
pop sound comes from speaker.

Change-Id: I7ad68caa88d7b3ff52ac1379fe6564de27d97777
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/16933
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-10 17:12:14 +02:00
Nico Huber 6dfffdc297 Makefile.inc: Fix make gitconfig for blobs repo
It's `.git/modules/3rdparty/blobs` now.

Change-Id: Ief12bb934332375a20f150afb568aef266924c9f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16946
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-10 13:46:02 +02:00
Elyes HAOUAS b23ed4e252 northbridge/intel/nehalem: Remove commented code
Change-Id: I2d40049a27f725f14acbc16438f0e6ea7cdd7329
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16879
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10 01:17:42 +02:00
Elyes HAOUAS ff25b6c35b northbridge/intel/i440bx: Remove commented code
Change-Id: I0dd8c32f1b9165fe8c449cee1c21a155a725c04f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16878
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10 01:17:14 +02:00
Elyes HAOUAS f10b5ff8a9 mainboard/kontron: Use C89 comments style & remove commented code
Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16908
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:39:31 +02:00
Elyes HAOUAS 8d94fbd999 mainboard/artecgroup: Use C89 comments style & remove commented code
Change-Id: Ia1e7f558bbc44001358339a522e59a2ef7c420fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16923
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:39:18 +02:00
Arthur Heymans aacd548c26 cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E
The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo
Processor on 65 nm Process" mentions cpu C-states substates which can
either be attained by adding a substate hint to the MWAIT/P_LVLx request
or automatically by setting some msr bits correctly.

This just sets the same msr bits as model_6fx to enable
dynamic L2 cache, C2E and C4E acpi cpu states.

The result is that when limiting a thinkpad x60 with a yonah T2400
cpu to the acpi cpu C2 state, the idle power usage drops from 18W to
14W. When the lowest C-state is set to C4 the idle power usage seems
to remain similar.

Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16901
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:37:50 +02:00
Elyes HAOUAS e7aeb2f602 src/northbridge/via: Remove commented code
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16898
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:36:47 +02:00
Elyes HAOUAS 83b9703505 northbridge/amd/agesa/family15*: Remove commented code
Change-Id: If372655700c18340d51368a39392560f664f4a45
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16896
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:36:28 +02:00
Elyes HAOUAS f8d399904c northbridge/amd/agesa/family14: Remove commented code
Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16895
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:36:18 +02:00
Elyes HAOUAS 4da1aa8561 northbridge/amd/amdk8: Remove commented code
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16893
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:36:06 +02:00
Hakim Giydan 11302f38cd libpayload: mvmap2315: Introduce timer driver
Testing: booted successfully.

Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-09 21:31:46 +02:00
Elyes HAOUAS 1a77fd3e36 northbridge/amd/lx: Remove commented code
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16891
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:31:11 +02:00
Elyes HAOUAS e809dd3a84 northbridge/amd/pi/00730F01: Remove commented code
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16890
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:58 +02:00
Elyes HAOUAS 6bc3b96831 northbridge/amd/amdmct/mct_ddr3: Remove commented code
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16889
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:46 +02:00
Elyes HAOUAS 59840d1dee northbridge/amd/agesa/family16kb: Remove commented code
Change-Id: Ic22f8a00e6009e104df8c4374067369ebbf90ee2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16888
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:35 +02:00
Elyes HAOUAS decf90e4eb northbridge/amd/agesa/family15rl: Remove commented code
Change-Id: I5f45a4cd5661140f57aa37e86cc8a34622da3de5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:23 +02:00
Elyes HAOUAS d13b147235 northbridge/amd/agesa/family10: Remove commented code
Change-Id: I7966f996a4291cc6b97b53aba59b43358de94e45
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16886
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:14 +02:00
Elyes HAOUAS e0ee4c87e8 northbridge/amd/amdfam10: Remove commented code
Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16880
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:03 +02:00
Alexander Couzens fd5c658871 ifdtool: use max_regions to reflect ifd header version
Change-Id: I71a12235196d478673d2816a9ee64f1373f3a63d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16935
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-09 19:10:01 +02:00
Alexander Couzens a81bef1bd6 ifdtool: promote max_regions as global
max_regions is set to the maximal regions based on the ifd version

Change-Id: I9fa5a4565f4dbd67b5c6df97756311560e2a18bc
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16934
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-09 19:09:23 +02:00
York Yang 913684cd2e soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled
When timestamp is enabled, the system hangs because the timestamp data 
is not yet available. Add a temporary work around that starts the 
timestamp after the FspInit() making this data available.

Verified on Intel Camelback Mountain CRB and ensured that system can 
boot to payload with timpstamp feature enabled.

Change-Id: I59c4bb83ae7e166cceca34988d5a392e5a831afa
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/16894
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 19:08:07 +02:00
York Yang ab5f3d1304 soc/intel/fsp_broadwell_de: Remove the enforced fsp1.0 APIs call sequence
The enforced FSP 1.0 APIs call was used to work around an fsp1.0 driver
issue.  As the issue has been addressed in fsp1.0 driver (Change 9780),
remove the enforced workaround. Otherwise will see error message
'FSP API NotifyPhase failed' in serial log.

Verified on Intel Camelback Mountain CRB and confirmed that the serial
log error message regarding the 'FSP API NotifyPhase failed' is gone.

Change-Id: Iafa1d22e2476769fd841a3ebaa1ab4f9713c6c39
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/16892
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 19:07:58 +02:00
Martin Roth f641779bac drivers/intel/wifi: Add depends on ARCH_X86
When compiling a non-x86 platform with DRIVERS_INTEL_WIFI enabled,
we get the build error:

src/drivers/intel/wifi/wifi.c:17:30: fatal error:
arch/acpi_device.h: No such file or directory

acpi_device.h only exists in the x86 architecture directory.

Change-Id: Id0e29558336bf44e638cfcb97c22f31683ea4ec7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16906
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-10-09 02:39:04 +02:00
PH Hsu 34a6537512 google/oak: Increase the driving strength for 4GB DRAMs
Some PVT units encountered DRAM calibration failure during
power on/off tests. The failure is caused by higher impedance
of the DRAM on those units. So increase the driving strength
for 4GB DRAMs.

BUG=chrome-os-partner:57392
TEST=run cold reboot 100 times on PVT units which have DRAM
calibration issue.

Change-Id: I8a329093db3f1def566e4b7afec3c4f4bfe44c6a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf1aa5ade856af433fa056f51a20d18553ae241d
Original-Change-Id: I0d1776cd1a5892d1f82e9bf414620d1ef6d29132
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/394451
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/16917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-08 16:41:03 +02:00