Commit Graph

10356 Commits

Author SHA1 Message Date
Alexandru Gagniuc 7efd5fda49 hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11
Hudson ASL files assume the USB power event notifications are mapped
to GPE 0xb. Since that GPE is not used on this board, map these events
to GPE11. This GPE is already handled in ACPI via Method(_L0B). We
adjust this method to also notify the XHCI controller at PCI 10:0.

Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:43 +02:00
Alexandru Gagniuc 44f2fab89a AMD hudson and yangtze boards: Let mainboard declare power button
The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
always had the wake source declared as GPE3. This is not the correct
wake source for all boards. On some laptops declaring a wake source is
not needed, as the wake mechanism is handled by the EC.

Move the declaration of the power button to mainboard ASL files, and
scope it as \_SB.PWRB . This also makes the naming consistent with the
examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
M6 1035dx is removed, as it is incorrect.

Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:34 +02:00
Edward O'Callaghan ce7a8024ff mainboard/asus/m5a88-v/devicetree.cb: Fix formatting
Strip incorrect comments pretaining to the superio, and replace spaces
with tabs.

Change-Id: Ib3f6094c552777552d0ec06e3236210ee2e7b05d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5562
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-21 18:17:39 +02:00
Alexandru Gagniuc 0a57e999b7 hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resume
It's not needed, and puts the EC back into APM mode. The EC does not
shut down during S3 sleep, so we don't need to re-initialize it.
Lid SMI will have been disabled in the switch to ACPI mode, don't
re-enable it.

Change-Id: I2c06df140f63427dac32ae095d29e68f64135358
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5555
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:46:26 +02:00
Alexandru Gagniuc cf1f9b6a5b southbridge/hudson: Remove redundant definitions of ACPI IO ports
The ACPI IO ports were defined twice, and used inconsistently. Only
keep one of the definitions for consistency.

Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:44:16 +02:00
Alexandru Gagniuc 991e951461 southbridge/amd/agesa/hudson: Refactor SPI controller driver
The SPI controller driver used numerical offsets to access SPI
registers, making it unreadable without the datasheet. Use less magic
and more #defines to improve readability.

Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5557
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:44:04 +02:00
Alexandru Gagniuc c38d991387 hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPI
This patch completes ACPI support for the lid switch. The lid SCI now
notifies the OSPM of the status change when the lid is closed or
opened, allowing system to suspend. The wake source is also declares,
and the system wakes when the lid is opened.

The system resumes successfully, but the display still does not come
back on.

Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5549
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:34:01 +02:00
Alexandru Gagniuc c4e7db51fc hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping table
Each GEVENT pins can be mapped to a specific GPE via the SCI map.
The default mapping is not appropriate for this laptop, so use the
AGESA functionality to map currently known events.

Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5548
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:33:39 +02:00
Alexandru Gagniuc a9a3661710 hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file
These definitions were scattered in a couple of files, and we risk
scattering them all over the place. Provide a common file for these
definitions.

Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5547
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:33:26 +02:00
Kyösti Mälkki 46b0951182 Move MAX_PHYSICAL_CPUS to AMD k8 and fam10
This was always AMD-only and it was never properly used with AGESA.

Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5540
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:04:07 +02:00
Kyösti Mälkki a6c525a7d5 AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
Following boards use cimx/sb700:
  amd/dinar
  supermicro/h8qgi
  supermicro/h8scm
  tyan/s8226

Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).

Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.

I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.

Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5539
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:03:55 +02:00
Kyösti Mälkki 35546deba6 AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1.

Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5538
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-20 20:03:46 +02:00
Kyösti Mälkki 9816392337 amd/torpedo: Remove unused Kconfig options
These are not used with cimx/sb900 vendorcode.

Change-Id: I489ee80c739b31edac649491497162c65316996e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5537
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:03:36 +02:00
Kyösti Mälkki 29c3e367da AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS
Match the definition of NODE_PCI() with get_node_pci(), so romstage
and ramstage agree of the PCI BDFs for nodes.

Note that all board have CONFIG_CDB = 0x18 and the maximum for
nodes = 8, so we always have (CONFIG_CDB + x) < 32.

Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5536
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:03:26 +02:00
Vladimir Serbinenko b1ccccc207 mainboard: New port Packard Bell LM85.
Change-Id: I8c1548470c605d06825fe35579879e806bf33542
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5271
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-04-20 18:47:19 +02:00
Edward O'Callaghan 5c97142419 drivers/elog: Fix implicit function declaration issue
Fix compilation. Relying on the pre-processor to condition an if
statement will lead to warnings of implicitly defined functions. To
solve this dilemma add symbols to resolve to at compile time.

Change-Id: Id0117528c5579cc1dec750a8a17a76fab4314b3f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5504
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 17:43:34 +02:00
Aaron Durbin 3bc6eb544c rmodule: add subsections to linker script
Depending on the compiler options, subsections of the form
of .section.subsection could be generated. Therefore, include
those subsections for .bss, .sbss, and .data.

Change-Id: I80dd64d8c62e7bc449ee2bbc0a22a941777e2ea6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5407
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-19 07:11:41 +02:00
Alexandru Gagniuc 7f09b754f9 hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method
Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5517
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:50:15 +02:00
Alexandru Gagniuc 5db38a38c9 hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey
Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5516
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:50:09 +02:00
Alexandru Gagniuc fa840676f5 ec/compal/ene932: Update to use coreboot EC-mainboard API
This patch implements a simple interface between the EC and mainboard
ASL code. This interface does not rely on the preprocessor, and
prevents name conflicts by scoping the interface methods. As this
interface is documented on the coreboot wiki, an in-tree documentation
is not provided.

Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5515
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-19 03:49:48 +02:00
Alexandru Gagniuc 91b6d3a6b9 hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"
There is only one lid switch, so it does not make sense to number it.
This naming is also consistent with the examples in the ACPI spec.

Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5545
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:14:35 +02:00
Alexandru Gagniuc 489ff7ef87 hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS
This is handled by generating an SMI when GEVENT22 goes low. This pin
is driven by the EC when the lid opens or closes. This SMI is
disabled when switching to ACPI mode, so ACPI OSes are not affected.

Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/171
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:58:50 +02:00
Alexandru Gagniuc 599d668cdd southbridge/hudson: Compile refactored SMI setup utilities in SMM
Refactor hudson_enable_gevent_smi() to allow configuring the interrupt
mode and trigger level. Move the utilities which are useful in SMM to
a separate file that is included in both ramstage and SMM. This is
useful for SMI handlers which need to enable or disable GEVENT SMIs
on-the-fly. A follow-up patch makes use of this infrastructure.

Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/170
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:58:39 +02:00
Wei Hu 2ad6ee9763 util/cbfstool: Fix "Bad segment type 53534220 Could not load payload".
The magic number mismatch was introduced by commit a8a133
(Add section header parsing and use it in the mk-payload step).

Change-Id: I73b0adb969816e9d130f19f48e175c57124e2f3a
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Reviewed-on: http://review.coreboot.org/5528
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-18 21:18:05 +02:00
Alexandru Gagniuc dbe6336f90 hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
Intercept the low battery SMI from the EC, and shut down the system
immediately. The EC only sends this SMI when the OS did not enable
ACPI mode, so ACPI OSes are not affected by this.
On the other hand, payloads such as GRUB or SeaBIOS will experience
the shutdown. This behavior is helpful for protecting the battery, for
example, when the OS fails to boot and we are stuck in the payload.
The low battery SMI is triggered at 10% charge, at which point the risk
of cell degradation exists.

Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:16:24 +02:00
Kyösti Mälkki f339086265 console: Simplify the enable rules
Consoles on CBMEM and USB have somewhat complex rules and dependencies
when they can be active. Use simple variables to test which stage
of boot is being built for each console.

Change-Id: I2489e7731d07ca7d5dd2ea8b6501c73f05d6edd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-18 16:41:09 +02:00
Kyösti Mälkki e8792be223 build rules: Identify build stage with simple variables
Provide simple environment variables telling which stage of boot is
being built. Also move this to arch-agnostic location.

Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5410
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-04-18 16:40:32 +02:00
Kyösti Mälkki efb0b51e62 console: Split ROMCC helpers
These are potentially useful with GDB or SerialICE too.
Also it reduces the amount of actual code we put in romcc_console.

Change-Id: Id8c56e979660ad9f4eef39c648f68c7ec60edfba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5339
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:40 +02:00
Kyösti Mälkki 4076072b6c console: Use romstage code for ramstage and SMM
Console is arch-agnostic and there is no need for separate
implementations for romstage and ramstage.

For SMM there is console only if DEBUG_SMI is selected.

Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:19 +02:00
Kyösti Mälkki fd95624dae console: Drop driver list in ramstage
This framework was only available in ramstage. So we had to define
console output functions separately for bootblock, romstage and SMM.
Follow-up patches will re-enable all the consoles removed here,
in a more flexible fashion, and with less lines-of-code and copy-paste.

Also the driver list is not in a well-defined order and some of the
loops could exit without visiting all drivers.

NOTE: This build has no console in ramstage.

Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5337
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:09 +02:00
Patrick Georgi aece3c931e msi/ms9652_fam10: minor Kconfig cleanup
SMP and IOAPIC shouldn't need to be redefined here, select is enough

Change-Id: I8a66374205b671498ce21b3f174af14e98dbfe48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5541
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-18 15:09:41 +02:00
Edward O'Callaghan f951d66d31 southbridge/sb800: Strip obsolete commentary
Change-Id: I5cd9e1fcf197eae966be710b2ab24f49c6885eb0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5529
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-18 11:51:36 +02:00
Kyösti Mälkki 43cb7ca922 AMD hudson yangtze: Drop MAX_PHYSICAL_CPUS in comments
Change-Id: I81de291da7b3db8d04a127d5a304b558f1c75b34
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17 23:56:33 +02:00
Alexandru Gagniuc fa4cb6d606 southbridge/hudson: Remove unused function set_sm_enable_bits()
This function isn't used on hudson, and seems to be copy-paste from
older southbridges. It is used in sb700 to enable or disable certain
PCI devices. On hudson, these configuration bits are moved to the PM
space.

Change-Id: I9b967a2d0a5dddc8341204dadeed90460251915c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5513
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 23:20:12 +02:00
Alexandru Gagniuc 09fe3f83c5 hp/pavilion_m6_1035dx: Remove code which dumps ACPI tables
Dumping ACPI tables in canonical form has very little value, and is
of questionable use except when debugging acpigen. Remove the code
which dumps the tables.

Change-Id: Id13c88cee8674b13e5cf5b5ed32c26283e586fd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5526
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-17 16:50:01 +02:00
Alexandru Gagniuc 73639e2717 hp/pavilion_m6_1035dx: Add SMI handler and handle EC requests
The EC may disable some functionality, such as Caps Lock LED and
battery charging if it never receives a command to go in APM mode. If
we start it in APM mode, then immediately switch to ACPI mode, it will
not get its SCIs serviced until an ACPI OS boots. If its SCIs are not
serviced, it may assume the OS has hung.

The way we solve this is to initalize the EC in APM mode, and only
switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE
command. The switch has to be handled in SMM.

Although we aren't yet processing SMIs from the EC, we are reading the
status in order to satisfy the EC that the event is handled.

Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5512
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 16:48:57 +02:00
Kyösti Mälkki 62abbe909d roda/rk9: Drop MAX_PHYSICAL_CPUS
Change-Id: I9c41cccf9058c48006b247aca705a3f869ae82a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5524
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17 08:20:24 +02:00
Alexandru Gagniuc 288c95882d southbridge/hudson: Add support for ACPI enable/disable via SMI
This enables the ACPI SMI command port in the FADT table, and sets up
the hardware accordingly. If we have SMI enabled, then we don't set
the SCI_EN bit at boot, causing the OS to send the ACPI_ENABLE
command, as required by the ACPI spec. This gives us a chance to hook
into the mainboard_smi_apmc() handler.

Change-Id: Ib4c63d55b3132578dcae48bfe2092d4ea35821dd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5511
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 04:42:44 +02:00
Alexandru Gagniuc 22d90e34f9 southbridge/hudson: Pass GEVENT SMIs to mainboard_smi_gpi()
Change-Id: Ifc368974a7a0dc0756431654fb89668e3846801a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5502
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-17 04:42:10 +02:00
Alexandru Gagniuc 2dbd08faf4 southbridge/amd/agesa/hudson: Add initial support for SMM
This sets up the infrastructure to handle SMIs generated by the Hudson
southbridge. An API for interfacing to mainboard handlers is not
defined at this point. A few functions are defined to allow mainboard
code to enable SMIs from GEVENT pins. These are the only functions which
I expect to be needed anytime in the foreseeable future.

SMIs are always acknowledged and cleared, as not clearing an SMI will
cause us to re-enter the SMI, effectively bricking the machine if a
southbridge-generated SMI without a handler occurs.

Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5494
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-17 04:41:49 +02:00
Alexandru Gagniuc 065b7da298 cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.

Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5501
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-16 23:42:19 +02:00
Alexandru Gagniuc 53072d869a cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).

There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.

Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5493
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16 23:42:00 +02:00
Alexandru Gagniuc 342ac64a5d southbridge/hudson: Use MMIO instead of PIO to access PM space
The MMIO region is set up by AGESA very early on, so we can use it to
access the PM register space in ramstage. 16-bit accessors are also
provided to simplify some setup tasks. 16-bit accesses are not
possible via PIO.
The pm2_iowrite/read accessors are removed, as they are not used.

Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5503
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16 22:29:33 +02:00
Kyösti Mälkki f3e82f7969 AMD AGESA fam15tn/fam16kb: Remove unused source files
Change-Id: I45084ffe84fef4dd43acea843d7c93a81c255472
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5523
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:39:11 +02:00
Kyösti Mälkki 72a1768aba AMD hudson yantgze: Drop MAX_PHYSICAL_CPUS
Not used with AGESA vendorcode.

Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5522
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:58 +02:00
Kyösti Mälkki fd478f92a4 AMD hudson yantgze: Drop APIC_ID_OFFSET
Not used with AGESA vendorcode.

Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5521
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:55 +02:00
Kyösti Mälkki 740862c7d3 AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLY
Not used with AGESA vendorcode.

Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5520
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-16 14:38:30 +02:00
Kyösti Mälkki aeb48934d4 AMD AGESA: Drop LIFT_BSP_APIC_ID
Not used with AGESA vendorcode.

Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5519
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:05 +02:00
Kyösti Mälkki ef5ce9a832 AMD AGESA: Drop AMDMCT
This config option is fam10 only.

Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5518
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-16 14:37:56 +02:00
WANG Siyuan 65f0dbc064 AMD Thatcher: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Thatcher.

Change-Id: I959721b4fd8787ac0824f9f873efd4788682eedb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/5359
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-16 13:35:51 +02:00