Commit Graph

10356 Commits

Author SHA1 Message Date
Kyösti Mälkki 04f5c4eca7 Build without ChromeOS
Change-Id: I1da636573eed62ce693b984917084643787c094b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3978
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:40:39 +02:00
Kyösti Mälkki 6578475d93 ChromeOS: Use common fill_lb_gpio()
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:40:11 +02:00
Kyösti Mälkki 9ab1c106c3 device: Conditionally bypass oprom execution
Builds with CHROMEOS can bypass VGA oprom when boot is not in
developer or recovery modes. Have the same functionality available
without CHROMEOS but with BOOTMODE_STRAPS.

Change-Id: I97644364305dc05aad78a744599476ccc58db163
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5595
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01 15:39:52 +02:00
Kyösti Mälkki ab56b3b11c ChromeOS: Remove oprom_is_loaded
A global flag oprom_is_loaded was used to indicate to
U-boot that VGA option ROM was loaded and run, or that
native VGA init was completed on GMA device.

Implement this feature without dependency to CHROMEOS option
and replace use of global variable oprom_is_loaded with call
to gfx_get_init_done().

Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:26 +02:00
Kyösti Mälkki 926a8d1262 google/stout: Fix build without ChromeOS
Currently we have no developer or recovery mode switches when
building without ChromeOS.

Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:05 +02:00
Kyösti Mälkki 5687fc9d21 Declare recovery and developer modes outside ChromeOS
Move the implementation for recovery and developer modes from
vendorcode/google/chromes to lib/.

Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01 15:38:41 +02:00
Kyösti Mälkki 580e5642a8 device: provide option to always load PCI option roms
Certain kernel drivers require the presence of option rom
contents because the board's static configuration information
is located within the blob. Therefore, allow a chipset/board to
instruct the pci device handling code to always load but not
necessarily run the option rom.

BUG=chrome-os-partner:25885
BRANCH=baytrail
TEST=Both enabling and not enabling this option shows expected behavior.

Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188720
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5594
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-05-01 15:38:11 +02:00
Kyösti Mälkki d540377390 console: Fix UART selection prompt
Without this change, removal of default UART_FOR_CONSOLE entries
under mainboard/ Kconfig will remove this option entirely from
created .config file.

Change-Id: I11422ddb8c51abca177f999936c995ae0c91c459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5626
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-30 23:47:28 +02:00
Duncan Laurie 93966e8592 baytrail: Add default _OSC method
This is needed to let the kernel know it can control everything
and not to disable features.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175629
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4939
Tested-by: build bot (Jenkins)
2014-04-30 23:12:03 +02:00
Duncan Laurie 053bd0753b baytrail: Add root bus resource regions
Populate the PCI mmio region from NVS TOLM variable.
Other regions are fixed.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175628
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4938
Tested-by: build bot (Jenkins)
2014-04-30 23:11:56 +02:00
Duncan Laurie 03ff2a242e baytrail: Add MCFG table to ACPI
This adds the PCI configuration region table to baytrail.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4937
Tested-by: build bot (Jenkins)
2014-04-30 23:11:46 +02:00
Duncan Laurie abab05cb3c baytrail: Clean up NVS region
There is a lot of NVS allocated to things that are not really
used.  Most of these are removed and some are moved around.
Thermals are expected to be handled with DPTF so I've removed
that bit of code but have not yet cleaned up the thermal zone.

I left in the SIO BARs since I think we will need those still
even though they may need work still.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4936
Tested-by: build bot (Jenkins)
2014-04-30 23:11:34 +02:00
Duncan Laurie 1f52f51f4e baytrail: Add function to read top of low memory
The top of low memory is also the start of the region where
PCIe resources are allocated.  This needs to be passed in
ACPI but is only readable from IOSF.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4935
Tested-by: build bot (Jenkins)
2014-04-30 23:11:21 +02:00
Duncan Laurie 7fbe20bd2c baytrail: Add reserved MMIO regions to ACPI
Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.

Add a region for the "abort page" documented in the EDS.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4934
Tested-by: build bot (Jenkins)
2014-04-30 23:11:11 +02:00
Duncan Laurie a90a59f5a3 baytrail: Fix XHCI problems and re-enable
- a few clock gating bits were set improperly and were preventing
the system from transitioning out of S0 state.
- the XHCC registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control.  This was causing memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver

Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4933
Tested-by: build bot (Jenkins)
2014-04-30 23:08:35 +02:00
Edward O'Callaghan 8199809079 mainboard/: Avoid including early_serial.c from w83627hf
Following the reasoning of:
dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c

Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5597
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30 19:06:47 +02:00
Kyösti Mälkki f385ba42e3 console: Move UART port defaults to mainboard
Correct selection of UART depends of board layout, not the CPU
internals, so default setting should originate from mainboard.

Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5618
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:43 +02:00
Kyösti Mälkki 48713a1bf7 console: Drop EARLY_CONSOLE option
We have means to easily disable a specific console in romstage if
necessary, so this global option makes little sense.

The option was initially introduced as a work-around for build issues
around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.

Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5607
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:20 +02:00
Kyösti Mälkki 28837c6b01 allwinner/a10: Hide SoC specific UART functions
If platform has a component coreboot has to communicate with using
one of the UARTs, that device would not be part of the SoC and
must not use functions specific to a10 UART.

Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5469
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:37 +02:00
Kyösti Mälkki 70342a7f51 uart: Support multiple ports
The port for console remains to be a compile time constant.
The Kconfig option is changed to select an UART port with index
to avoid putting map of UART base addresses in Kconfigs.

With this change it is possible to have other than debug console
on different UART port.

Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5342
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:05 +02:00
Rudolf Marek a8d089d3ac towiki.sh Move vendor link to the first column.
It is not easy to see that there are two links,
one to coreboot wiki and second to the vendor page.
This change moves the vendor page link to the vendor
column, separating it nicely.

Change-Id: I3063be476231d04f833350043010a6e0001697e7
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/5593
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:39:19 +02:00
Paul Menzel 68eff4fb1c lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in comment
$ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g'

Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5325
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:23:52 +02:00
Andrew Wu b67e9a1acd crossgcc: Support OSX 10.9 built-in tar utility program.
Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in
tar program is bsdtar 2.8.3. bsdtar can build crossgcc toolchain.
Modify buildgcc to support tar in OSX 10.9 (uname = Darwin).

Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/5598
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:23:10 +02:00
Edward O'Callaghan dfa8a32f1f src/mainboard/asrock/e350m1: Properly indent devicetree.cb
Trivial: clean up spaces to tabs to properly indent devicetree.cb

Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29 20:54:03 +02:00
Edward O'Callaghan 178a60b4b3 mainboard/kontron/986lcd-m: Remove a duplicate header
Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5602
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29 20:18:52 +02:00
Paul Menzel 47a14b15cb util/board_status/board_status.sh: set its executable flag
Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5171
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-29 17:57:41 +02:00
Kyösti Mälkki bb6c2162d1 AGESA SPI: Fix Kconfig options
Option AMD_SB_SPI_LEN leaked to non-AMD configs.
Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME.

Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29 17:31:40 +02:00
Kyösti Mälkki 88e518f4bc SPI: Use common dependency in Kconfig
Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-29 17:31:03 +02:00
Edward O'Callaghan 9e308b9955 superio/winbond/w83627ehg: Convert romstage to generic component
Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5589
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 20:14:58 +02:00
Edward O'Callaghan 959adc3fcf mainboard/tyan/s8226: Remove redundant sio header
Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 19:40:23 +02:00
Edward O'Callaghan ffe460d77a superio/winbond/w83627dhg: Convert romstage to generic component
Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 19:22:14 +02:00
Edward O'Callaghan dbbc136c83 mainboard/asrock/e350m1: Avoid including early_serial.c
Use generic winbond romstage serial init symbols instead of model
specific implementation. We do this on a case by case basis as some
boards are ROMCC and so need to #include .c files. This is a step to
migrate non-romcc boards to a more generic superio framework.

Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5591
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 18:59:39 +02:00
Edward O'Callaghan 5a032c628b superio/winbond/*: Provide common romstage component
Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5587
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 18:58:51 +02:00
Kyösti Mälkki 2458f42b27 AMD: Add common header file for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-28 18:36:35 +02:00
Edward O'Callaghan cf7b498908 superio/fintek/*: Factor out generic romstage component
The romstage of Fintek Super I/O's is identical, leading to replication
of essentially the same code prone to bitrot. Herein we consolidate the
early pre-ram UART initialisation code into fintek/common, rather we
leave the exceptions to be implemented under model/.

More precisely we provide a well documented version of early_serial.c
under fintek/common and select by way of Kconfig as a generic romstage
component to Super I/O support. We leave future Super I/O's the option
to implement `non-standard` initialisation code should such a (unlikely)
need araise. A primary advantage is that new support for romstage serial
is now trival to add. We also provide some Kconfig documentation while
here.

Change-Id: I3c62561558a62ece944a167ba302fb7076bba001
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5575
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 18:22:11 +02:00
Kyösti Mälkki 4566d2e7cd uart8250io: Fix build with DEBUG_SMI
Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-26 15:09:07 +02:00
Edward O'Callaghan 6bedc27426 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
Alignment-agnostic encode/decode bytestream to/from little/big endian.

The le16enc(), le16dec(), le32enc(), le32dec() functions encode and
decode integers to/from byte strings on any alignment in big/little
endian format. See BYTEORDER(9).

Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5198
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-26 15:03:43 +02:00
Patrick Georgi f33782fb86 lippert/hurricane-lx: Kconfig cleanup
A Kconfig option defined instead of selected that really comes from
somewhere else.

Change-Id: I8730d12ed053520b794655e943c93583c441f3f1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5542
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 14:13:58 +02:00
Edward O'Callaghan 6d51f6b2e8 superio/fintek/*: Fix header style
Remove some redundant includes. Fix repetitiveness in include guards and
strip some misplaced tabs for whitespaces.

Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5572
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:48:36 +02:00
Furquan Shaikh 20f25dd5c8 Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:27:09 +02:00
Furquan Shaikh 817149643c Get rid of HAVE_INIT_TIMER config option
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use a stub for init_timer in
places where we do not have any init_timer defined. Thus, remove the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include a stub_timer if required.

Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 13:25:28 +02:00
Edward O'Callaghan ea2900bd6c superio/ite/it8673f: Remove poor implementation
Following the reasoning of:
HASH superio/ite/it8705f: Remove poor implementation

Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5568
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:10:54 +02:00
Edward O'Callaghan 45b7b5af76 superio/ite/it8705f: Remove poor implementation
This super io support is poorly implemented and would not work for all
boards since it hardcodes values. Since there are no users of it, remove
for now pending a fresh reimplementation from scratch.

Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5566
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:08:53 +02:00
Edward O'Callaghan 5c41ee69ef superio/ite/it8716f: Rewrite from hardcoded base addr
Following the same reasoning as:
HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr
Removing hard coded magics and expose sio pnp api in romstage.

Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5565
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:06:15 +02:00
Edward O'Callaghan 03ad2a26b0 superio/ite/it8721f: Rewrite from hardcoded base addr
Rewrite early_serial.c implementation to honour a passed base address in
device_t, removing any hard coding of values. We also expose early sio
init functions as romstage symbols to avoid falsely #including
"early_serial.c" in romstage.c of board support.

Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5561
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 12:57:04 +02:00
Edward O'Callaghan 392de45ae2 mainboard/*: Remove DUMP_ACPI_TABLES from amd boards
Dumping the ACPI tables in this way has limited use, is not likely to be
used and is poorly implemented. There are much more sophisticated tools
available on Linux for debugging ACPI as such this code is outside the
scope of coreboots 'bring up the hardware only' philosophy.

A more generic implemention could be done with hexdump() in coreboot
proper following on from this cleanup.

Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-26 12:48:46 +02:00
Kyösti Mälkki d6060b7142 usbdebug: Add BeagleBone Black
Avoid some confusion as the selection of "BeagleBone" is not compatible
with the product "BeagleBone Black".

Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4289
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-22 15:49:26 +02:00
Kyösti Mälkki 147f703aa9 Drop drivers/generic/debug
Not very popular nor useful nowadays.

Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4554
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-22 13:42:48 +02:00
Alexandru Gagniuc 86777e36b3 southbridge/hudson: Initialize ACPI IO ports separate of FADT
The ACPI IO ports, and the respective SMI (for HAVE_SMI_HANDLER), were
initialized when the FADT table was written. This works well on a cold
boot, but the ACPI ports are not initialized on S3 resume, as ACPI
tables are not written. This will not work on S3 resume if the default
ports are not what we set them, or if AGESA sets them to some other
value.

To solve this, move the port configuration to southbridge chip init.

Change-Id: Ib4043f0fa5e20f08d320acd12ce84d4d789cd035
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5559
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:33:01 +02:00
Alexandru Gagniuc cf38facbd2 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
The PCIE PME pin from the APU is connected to GEVENT8, but the
northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
accordingly.

Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5556
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:51 +02:00