This does not exist anywhere in the entire coreboot tree. Drop it.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
With conversion to variant structure complete, remove temporary guards
inserted to help validate the move.
With this change, all P2B family boards (currently p2b and p2b-ls)
share the same S-state declarations.
TEST=No apparent ACPI regression observed on p2b-ls.
Change-Id: Ibd6e49adeae2a42800ee5bfd74b3850eb19843a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fold this last ASUS 440BX board into the P2B family, while bringing in
some changes:
- Devicetree becomes overridetree.
- Remove non-existent IR device and disable ACPI device on Super I/O to
match OEM firmware.
- Add SB GPO settings from OEM firmware to devicetree. This disables
the SPD enabling magic this board needs. By moving the enabling part
to bootblock the hacky enable_spd hook can be eliminated.
- Initialize the serial port in bootblock, like the other boards.
Boot tested on hardware.
Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It is only used with the Lenovo-specific H8 EC code.
Change-Id: I596d4d19277555894ab728e32a44e34a5a21e21d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
There's no reason not to.
Change-Id: I12c9e0f66c437d8add5c4096fd2a5e747d082799
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The SVID functionality is not used on this mainboard. Turn it off.
Change-Id: Iea891975b32d24f54edec9d8c36391ec60a37d0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
SB-TSI is specific to AMD platforms, but this is an Intel board.
Change-Id: I5eb7e3bc920103279dfca3a9ec14a41666404993
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40738
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board uses the pin for Deep S5, but the code was setting 3VSBSW.
Change-Id: I81c865358002e6af500658efea851ab8c8202950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
These boards have the same issue as [27272]:
Currently, two power buttons are exposed in ACPI, and detected by the
operating system.
> As per the ACPI specification, there are two types of power button
> devices:
> 1. Fixed hardware power button
> 2. Generic hardware power button
>
> Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
> is not set in FADT by the BIOS. This device has its programming model
> in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
> power button device by default if the power button FADT flag is not
> set.
>
> On the other hand, generic hardware power button can be used by
> platforms if fixed register space cannot be used for the power button
> device. In order to support this, power button device object with HID
> PNP0C0C is expected to be added to ACPI tables. Additionally,
> POWER_BUTTON flag should be set to indicate the presence of control
> method for power button.
>
> [i440BX] mainboards implemented the generic hardware power button in
> a broken manner i.e. power button object with HID PNP0C0C is added to
> ACPI however none of the boards set POWER_BUTTON flag in FADT. This
> results in Linux kernel adding both fixed hardware power button as
> well as generic hardware power button to the list of devices present
> on the system. Though this is mostly harmless, it is logically
> incorrect and can confuse any userspace utilities scanning the ACPI
> devices.
Hardware tests on the P2B-LS shows the generic hardware power button
is not working anyway - with FADT power button flag set, the board
could not power off with the button.
This change removes the generic hardware power button from all P2B
mainboards and relies completely on the fixed hardware power button.
TEST=Booted on P2B-LS, Linux detects only fixed hardware power
button, button still powers off.
[27272]: https://review.coreboot.org/27272
Change-Id: I0f5b7aaf32366360de3cce58cd742651a2bb46ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replicate the GPO configurations from OEM BIOS, obtained via inteltool.
Among the GPOs are termination controls for the onboard SCSI buses.
TEST=read/write Maxtor Atlas 10k3 18GB HDD connected to Ultra2 LVD port
Change-Id: I86183acd8e1a830d7639c21ec179fbdbe937f8ee
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
Actually, I have the PLUS variant, but they use the same PCB. The only
difference is the capacitor quality.
Working:
- Both DIMM slots
- PS/2 keyboard
- S3 suspend/resume
- Rear USB ports
- Integrated graphics (libgfxinit)
- VGA
- All PCIe ports
- Realtek GbE (coreboot must set the MAC address)
- SATA ports
- Native raminit
- Flashing with flashrom
- Rear audio output
- VBT
- Arch Linux using CorebootPayloadPkg
Untested:
- PS/2 mouse
- The other audio jacks
- EHCI debug
- Front USB headers
- Non-Linux OSes
Change-Id: I385ee72673202d896041209ff2911995307cb6af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All variants will use the same lid/thermal-polarity config as a result,
which looks the same for all recently boot-tested variants anyway.
Change-Id: Iaaae4eae41ab0037e72375b255d9d1c3eca8d383
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33919
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like the guard was dropped by mistake.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33916
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These comments exist in other buildOpts.c files, but not in this one.
Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This makes it easier to know which files are being included.
Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S.
This improves diff results, which is convenient for debugging.
Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33913
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sb/intel/i82371eb/isa.c has code that fills this path with CPU info.
Because it was not declared in the DSDT, Linux kernel 4.4.18 as used in
Slackware 14.2 complains.
Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With this bootblock messages are transmitted over serial too.
TEST=Serial messages transmitted normally on asus/p2b-ls.
Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I92d0dc8d93a8b409959d79834ccb5093224285cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to clobber the registers with
garbage in ramstage.
Tested, my Asus P5G41T-M LX still boots and it does not need a full
reset on almost every reboot.
Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all GPIO4 pins on the SuperIO are configured as outputs.
Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to rewrite their values in
ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
