Commit graph

92 commits

Author SHA1 Message Date
Vladimir Serbinenko
a2a906e47a Consolidate intel vga int15 hooks
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6820
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05 22:48:49 +02:00
Vladimir Serbinenko
02d674ac2f azalia: Use convenience macros throughout
Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05 00:12:11 +02:00
Vladimir Serbinenko
f99a62b65e Remove dead video.asl
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6730
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22 20:27:58 +02:00
Vladimir Serbinenko
6a3a8ce1a8 azalia: Move shared variable to separate file
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6695
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-18 15:06:44 +02:00
Martin Roth
73d5d4cb11 mainboard/XXX/YYY/dsdt.asl: Whitespace fix
Use tab between "COREBOOT", and comment.

This fix was requested in 90957f88 -
"mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000"

Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6601
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18 02:24:02 +02:00
Aaron Durbin
a0a3727dbb intel/cpu: rename car.h to romstage.h
This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.

Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-15 03:44:46 +02:00
Edward O'Callaghan
1ab2027955 Intel: Add common header file for CAR setup
When passing '-ffreestanding' the 'main' romstage.c may no longer
necessarily be considered the entry point.

From the C specification in 5.1.2.1 Freestanding environment;

"In a freestanding environment (in which C program execution may take
place without any benefit of an operating system), the name and type of
the function called at program startup are implementation-defined."

Clang complains about these being missing as Clang is somewhat more
strict about the spec than GNU/GCC is. An advantage here is that a
different entry-point type-signature shall now be warned about at
compile time.

Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5872
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-14 15:12:26 +02:00
Vladimir Serbinenko
5fc04d1fdd sandy/ivybridge: Make UMA size configurable.
Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6470
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-03 13:44:40 +02:00
Edward O'Callaghan
cb70f79126 mainboard: Trivial - drop trailing blank lines at EOF
Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6291
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18 14:42:47 +02:00
Edward O'Callaghan
1f9653a1bc src/superio/ite/it8772f: Separate mainboard from SIO at obj level
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.

Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18 07:42:27 +02:00
Edward O'Callaghan
52f7043024 mainboard,ASL: Trivial - drop trailing blank lines at EOF
Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6292
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17 02:18:23 +02:00
Edward O'Callaghan
7974471e37 mainboard: Trivial - drop trailing blank lines at EOF
Change-Id: I05d6d22664155ac8478e665733f816776e277c22
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6200
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:54:47 +02:00
Edward O'Callaghan
4b7910635d mainboard: Make use of ARRAY_SIZE macro in hda_verb.h
We have the macro, let us be sure to make use of it.

Change-Id: I8dc5ca580c7485e3cce7ebc29189a452de52b1b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6193
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-08 07:55:29 +02:00
Kyösti Mälkki
d9cf38fdcb sandy/ivy boards: Switch to use DYNAMIC_CBMEM
Like with other more recent boards already using DYNAMIC_CBMEM,
the pointer to TOC is no longer stored in GNVS for ACPI.

Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:11:59 +02:00
Kyösti Mälkki
c3ed88636a intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:52 +02:00
Kyösti Mälkki
6722f8da40 sandy/ivy boards: Use acpi_s3_resume_allowed()
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6063
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:51:16 +02:00
Kyösti Mälkki
a0b4a8d819 ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.

Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-18 20:37:34 +02:00
Edward O'Callaghan
1b3acb13e4 superio/ite/it8772f: Move towards removing #include .c
Move samsung/stumpy board towards generic romstage component and away
from poorly written hard-coded model specific Super I/O component. This
is an incremental step towards getting obj-level abstraction between
board and Super I/O.

Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5899
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:35:38 +02:00
Edward O'Callaghan
b27d3602e0 mainboard/samsung/stumpy: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I6c5cc46385581d6b69d20f6bc9b016b799765d9e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:42:03 +02:00
Kyösti Mälkki
f7bfc34942 intel: Remove GFXUMA and related global variables
Remove use of global variables uma_memory_base and uma_memory_size
from builds with Intel northbridges, as these variables can be kept
within the chipset or even as stack locals.

Intel platforms have no functional implemenation for option GFXUMA.
If we did implement some choice between external and integrated graphics,
it needs to be named in less obscure fashion.

Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 17:20:13 +02:00
Kyösti Mälkki
a6b6172ae3 Add aliases for Chromebooks in board_info
This defines new board_info entry 'Vendor name' to be displayed in place of, or
in addition to, the CONFIG_VENDOR string 'Google'.

Also flag these as flashrom accessible SPI without socket. Instructions to
disable flash write-protection can be found at Chromium developer documentation.

Change-Id: I69791a091417a80d01e0ba2c6462417730a07be0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 14:57:54 +02:00
Kyösti Mälkki
5c4b8483d2 ChromeOS boards: Always build code for bootmode straps
Leave it under BOOTMODE_STRAPS to control whether these have
any functional meaning on the build.

Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 16:26:58 +02:00
Kyösti Mälkki
e3ddee0437 Rename from save_chromeos_gpios() to init_bootmode_straps()
This feature is no longer specific to ChromeOS builds.

Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:16 +02:00
Kyösti Mälkki
ff402e3aeb ChromeOS boards: Use explicit include of chromeos.c
Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:05 +02:00
Furquan Shaikh
fd33781fbf Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.

Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 00:25:20 +02:00
Kyösti Mälkki
6578475d93 ChromeOS: Use common fill_lb_gpio()
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:40:11 +02:00
Kyösti Mälkki
ab56b3b11c ChromeOS: Remove oprom_is_loaded
A global flag oprom_is_loaded was used to indicate to
U-boot that VGA option ROM was loaded and run, or that
native VGA init was completed on GMA device.

Implement this feature without dependency to CHROMEOS option
and replace use of global variable oprom_is_loaded with call
to gfx_get_init_done().

Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:26 +02:00
Kyösti Mälkki
4c686f2106 OxPCIe uart: Split PCI bridge control
None of the PCI bridge management here is specific to the PCI UART
device/function. Also the Kconfig variable defaults are not globally
valid, fill samsung/lumpy with working values.

Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5237
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:29:45 +02:00
Kyösti Mälkki
afa7b13b93 uart: Redefine Kconfig options
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.

Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.

Removes:
  CONSOLE_SERIAL_UART
  HAVE_UART_IO_MAPPED
  HAVE_UART_MEMORY_MAPPED

Renames:
  CONSOLE_SERIAL8250     ->  DRIVERS_UART_8250IO
  CONSOLE_SERIAL8250MEM  ->  DRIVERS_UART_8250MEM

Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:24:43 +02:00
Paul Menzel
35a4901d3a mainboard/*/*/ec.c: Do not include chromeos/chromeos.h
It's not needed and causes build failures without CONFIG_CHROMEOS.

Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd
Reported-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5398
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-28 19:28:31 +01:00
Alexandru Gagniuc
76e25b66ae google boards: Do not hardcode location of spd.bin
spd.bin can reside anywhere in CBFS, and we only use CBFS APIs to
access and read it. As such, there is no need to hardcode it, and it
can collide with mrc.bin or mrc.cache on some boards. Do not use a
specific position for spd.bin, but instead let cbfstool find the
optimal placement.

Change-Id: I496094d3c0de708813494095b7ac4be8addb4112
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12 23:37:24 +01:00
Vladimir Serbinenko
52884ad161 board_info.txt: Classify almost all remaining boards.
Based on info from commit messages (most devel/eval boards are mentioned
as such in commit message) and information from vendor sites (mostly based
on form factor).

Classification for siemens/sitemp_g1p1 is based on info by Nico Huber.

For Google boards based on info from ML posted by Aaron Durbin.

Remaining unclassified board is:
google/pit

For which very little info is available publically.

Change-Id: I12dfff4c629811a48cfc77be27bdc5081530b8f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4759
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-22 22:05:39 +01:00
Kyösti Mälkki
2d8520b275 CBMEM: Replace cbmem_initialize() with cbmem_recovery()
The replacement function confirms CBMEM TOC is wiped clean on power
cycles and resets. It also introduces compatibility interface to ease
up transition to DYNAMIC_CBMEM.

Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4668
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-01-22 20:54:57 +01:00
Vladimir Serbinenko
4333071e23 board-status: Add board_info.txt extracted from wiki.
board_info.txt is a file to be used by board-status to add
some useful info to the generated table like flash chip type.
This series is autogenerated from wiki page Supported_Motherboards.

Change-Id: Ie2bda900713ef4883134477163320936c84c34f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4701
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-19 01:35:03 +01:00
Kyösti Mälkki
78938481eb Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
Delay the copying of MRC cache data from CAR to CBMEM until after
sdram_initialize() returns and cbmem_initialize() completes.
Calling cbmem_initialize() twice would complicate the decision logic
of when CBMEM area needs to be wiped clean.

Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4666
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:33:54 +01:00
Vladimir Serbinenko
6d6298dddc ibexpeak / bd82x6x: Make SATA mode user-visible option.
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.

As per comments
"ide_legacy_combined # TODO: Does nothing since
		      generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.

Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:03:23 +01:00
Vladimir Serbinenko
1287416822 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
Number one reason to use cbfs_get_file was to get file length.
With previous patch no more need for this.

Change-Id: I330dda914d800c991757c5967b11963276ba9e00
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4674
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:58 +01:00
Vladimir Serbinenko
b32816e9a5 Remove PCI_ROM_RUN option
The main purpose of option rom is to supply int* handlers.
But supplying those is outside of coreboot scope and if someone needs those
they should run SeaBIOS anyway which runs the option roms wonderfully.

Running VGA oprom is kept because they're needed to init graphics.

This patch still keeps the options to include the option roms to make them
available to SeaBIOS.

Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-24 14:40:49 +01:00
Kyösti Mälkki
b67d99c01a lumpy: Fix build without ChromeOS
Change-Id: I1a59405499deceed7df01a03834be72830e6578f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-04 20:11:12 +01:00
Kyösti Mälkki
b1b9c93f7c Add option to disable ChromeOS
Those building Chromebook firmware from coreboot git might be more
interested in building without ChromeOS extras.

Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3977
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02 22:28:54 +01:00
Stefan Reinauer
454744fd86 Unify and clean up remaining INT15 handlers
Some handlers still had 2 variants, others were
incorrectly guarded by CONFIG_ variables. This
patch straightens them out.

This does not touch the siemens/sitemp_g1p1 which
provides an interestingly complex solution for the
int15 handler.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I5d74fdf7c2ab1faa96ebc2b5ca5c69398449b069
Reviewed-on: https://gerrit.chromium.org/gerrit/48979
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4140
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:03:58 +01:00
Duncan Laurie
0edc22490a smi: Update mainboard_smi_gpi() to have 32bit argument
With the LynxPoint chipset there are more than 16
possible GPIOs that can trigger an SMI so we need
a mainboard handler that can support this.

There are only a handful of users of this function
so just change them all to use the new prototype.

Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49530
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4145
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 07:40:22 +01:00
Kyösti Mälkki
f8bf5a10c5 Revert "CBMEM: Always have early initialisation"
This reverts commit de1fe7f655.

While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.

Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14 17:16:22 +02:00
Kyösti Mälkki
cbf5bdfe67 CBMEM: Always select CAR_MIGRATION
If romstage does not make cbmem_initialize() call, linker should
optimize the code for CAR migration away.

This simplifies design of CBMEM console by a considerable amount.
As console buffer is now migrated within cbmem_initialize() call there
is no longer need for cbmemc_reinit() call made at end of romstage.

Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:34:55 +02:00
Kyösti Mälkki
de1fe7f655 CBMEM: Always have early initialisation
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.

If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.

Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:26:54 +02:00
Kyösti Mälkki
3d45c40776 timestamps: Stash early timestamps in CAR_GLOBAL
Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3910
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:44 +02:00
Kyösti Mälkki
e28bd4ade6 timestamps intel: Move timestamp scratchpad to chipset
This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.

Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:02 +02:00
Stefan Reinauer
dedcc78ff4 Fix up Stumpy/Lumpy PEI data for system agent r6
Change-Id: I79937fd1671af23184ab830d5ba6242c8067d944
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3831
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28 23:38:39 +02:00
Stefan Reinauer
0aede1185b Drop unused EXTERNAL_MRC_BLOB
The Kconfig variable EXTERNAL_MRC_BLOB is not used.
Drop it.

Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3829
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-31 22:02:41 +02:00
Kyösti Mälkki
fbdb085549 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with SandyBridge and IvyBridge. To enable MMIO style access,
add explicit PCI IO config write in the bootblock.

Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3576
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:06 +02:00