Commit Graph

20424 Commits

Author SHA1 Message Date
Tobias Diedrich cee930a39b lenovo/s230u: Add Thinkpad Twist (S230U)
Created using autoport plus some manual work and copying from G505S to
account for the non-H8 EC.

This model uses the same ENE KB9012 EC as the G505S.

Tested:
- Mainboard variant with 8GB Elpida DDR3
- SeaBIOS payload
- Booting into Linux 4.9.6 with Debian/unstable installed on the
  internal HDD/SDD slot
- Native raminit
- Both native VGA init and option rom VGA init
- Basic TPM functionality (auto-detection and RNG)
- Battery status readout
- Basic ACPI functions (power button event; power-off; reboot)
- thinkpad-acpi hotkey functions
- thinkpad-acpi LED control (red thinkpad LED)
- Suspend to RAM and resume works
- Mini displayport output works

Known issues:
- Patches needed for EC battery support
  https://review.coreboot.org/#/c/18348/
  https://review.coreboot.org/#/c/18349/
- No thermal zone since temperature sensing is not H8-compatible
  and needs to be reverse engineered.

Not tested:
- msata/wwan (probably works)

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c
Reviewed-on: https://review.coreboot.org/18351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-02-20 18:21:56 +01:00
Furquan Shaikh 97535558f1 mainboard/{google,intel}: Change config option selection
Change config option selection from "config xyz default y" to "select
xyz" if the config option has no dependencies.

BUG=None
BRANCH=None
TEST=Verified that config option selection remains unchanged.

Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18400
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20 05:08:27 +01:00
Furquan Shaikh abd5d1d35c mainboard/google/reef: Remove config DRIVERS_GENERIC_GPIO_REGULATOR
Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18399
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20 05:07:28 +01:00
Mario Scheithauer 480eab0da9 siemens/mc_apl1: Set MAC address for all available i210 MACs
This mainboard uses two i210 Ethernet controller. Therfore we enable the
usage of the i210 driver and have to provide a function to search for a
valid MAC address for all i210 devices by using Siemens hwilib.

Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18380
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-20 04:47:53 +01:00
Paul Menzel 2a4a452abc ec/lenovo: Add guards to fix build errors without SMBIOS
Not selecting the Kconfig option `GENERATE_SMBIOS_TABLES` the build
fails with the error below.

```
    CC         ramstage/ec/lenovo/h8/h8.o
src/ec/lenovo/h8/h8.c:201:2: error: unknown field 'get_smbios_strings' specified in initializer
  .get_smbios_strings = h8_smbios_strings,
  ^
src/ec/lenovo/h8/h8.c:201:2: error: initialization from incompatible pointer type [-Werror]
src/ec/lenovo/h8/h8.c:201:2: error: (near initialization for 'h8_dev_ops.read_resources') [-Werror]
cc1: all warnings being treated as errors
```

So add the appropriate preprocessor guards to fix the build error.

Change-Id: I3baed452d422539a805c628a8c4a6a8c2a809317
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17770
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-02-20 04:46:49 +01:00
Robbie Zhang 18792314d7 arch/x86: add functions to generate random numbers
Using x86 RDRAND instruction, two functions are supplied to
generate a 32bit or 64bit number.

One potential usage is the sealing key generation for SGX.

BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.

Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20 04:46:10 +01:00
Teo Boon Tiong f296ce91b9 soc/intel/skylake: Expand USB OC pins definition to support PCH-H
Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.

Changes is being verified and booted to Yocto with Saddle Brook.

Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/18364
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20 04:44:47 +01:00
Matt DeVillier c97e042a9b lynxpoint/broadwell: fix PCH power optimizer
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.

The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.

Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output

Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18385
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20 04:44:22 +01:00
Matt DeVillier ee6a612eb2 Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.

This reverts commit 0f2025da0f.

Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18384
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-20 04:44:13 +01:00
Denis 'GNUtoo' Carikli efd9dee646 board-status: Add README
It explains the prerequisites to run the script, some
background on how to setup the computer running the script,
and the board it gathers the information from.

That information is too long to fit inside the script's
help.

Change-Id: Iecba7310ff1583149c02728e955716775bcbbdc4
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/6660
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-20 04:43:39 +01:00
Matt DeVillier 4b8252ed76 google/slippy: consolidate variants' common mainboard.asl code
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron).  This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function  when they were originally upstreamed.

See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device

Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18368
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-20 04:43:23 +01:00
Elyes HAOUAS 75da1fb2ba nb/i945/raminit: sdram_set_channel_mode Test if DIMM slot 3 is populated
Add a test in case we have a DIMM2 not populated but DIMM3 is.

Change-Id: I14f82afe03884740570838e7b2771233356c518d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18386
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-20 04:42:47 +01:00
Martin Roth f797a1ac6a riscv: Suppress invalid coverity errors
Coverity is detecting 'sp' as a variable which has not been initialized.
This is obviously not correct, so this patch *TRIES* to mark it as false

I'm not positive that this will work because the annotation needs to go
on the line above the error, but this error is inside of a # define.

Does the whole #define count as one line?  Can it go on the line
above the #define in the .h file?  Does it have to precede every line
where the #define is used?  The documentation doesn't make this clear.

Should suppress coverity issues: 1368525 & 1368527
uninit_use: Using uninitialized value sp.

Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18247
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-02-20 04:40:01 +01:00
Martin Roth 98641b92e7 src/drivers/pc80: Update vga_font_8x16.c to be non-binary
Previously, the file -i command identified vga_font_8x16.c as
application/octet-stream; charset=binary

Now it identifies as:
text/x-c; charset=us-ascii

- Remove non-ascii characters

Change-Id: I6b513e6457a31828a6e94c954a7e2e7ee18fd4d6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18372
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-02-20 04:39:40 +01:00
Duncan Laurie c86fa6d975 google/eve: Set rise/fall timing values for I2C bus 1
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.

BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope

Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18396
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-20 04:29:35 +01:00
Duncan Laurie 6c8238521e google/eve: Fix FPC support
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.

GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated.  Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.

GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.

Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.

BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS

Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18395
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-20 04:29:25 +01:00
Duncan Laurie 25c7d9342b soc/intel/skylake: Disable s0ix if not enabled in devicetree
There is an enable_s0ix config option in the devicetree that should
be used to disable it when not set:

- do not export C8/C9/C10 C-states in _CST
- do not enable SLP_S0 in FSP

BUG=chrome-os-partner:58666
TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
instead of 6 and that it no longer attempts to enter C10

Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-19 21:39:02 +01:00
Duncan Laurie c9db384ea4 drivers/spi/acpi: Add additional generic ACPI support
Add support for more ACPI features in the generic SPI ACPI
driver so it can be flexible enough to support more devices,
or devices in different configurations.

- add a wake pin
- add support for using IRQ GPIO instead of PIRQ
- add power resource support with enable and reset gpios

BUG=chrome-os-partner:61233
TEST=ensure existing SSDT generation is unchanged,
and test that new features generate expected code

Change-Id: Ibe37cc87e488004baa2c08a369f73c86e6cd6dce
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18393
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-19 21:37:55 +01:00
Duncan Laurie 4f31d5c2ce acpi_device: Add macros for GPIO interrupts
Add individual macros for the various interrupt types so
they can be used in devicetree.

BUG=chrome-os-partner:58666
TEST=nothing uses this yet, will be used in an upcoming commit

Change-Id: I2a569f60fcc0815835615656b09670987036b848
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18392
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-19 21:34:47 +01:00
Duncan Laurie bd73dbbc38 acpi_device: Move power resource function to generic code
Move the function that adds a power resource block from
i2c/generic to the acpi device code at src/arch/x86/acpi_device.c
so it can be used by more drivers.

BUG=chrome-os-partner:61233
TEST=verify SSDT table generation is unchanged

Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18391
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-19 21:34:12 +01:00
Arthur Heymans f9d5308690 mb/lenovo/t400: Implement hybrid graphic in romstage
The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work
for t400/t500.
Replace it with a custom romstage implementation.

Tested on Lenovo T500 with dual graphics:
* Intel Native GFX init
* AMD VBios
* GNU Linux 4.8.13
* SeaBios as payload
* Discrete is working (44 W)
* Integrated is working (24 W)
* Switchable is working (34 W)
** Both GPUs are enabled, with Intel being connected to the panel
** DRI_PRIME allows to use AMD GPU
** ACPI doesn't seem to work (no vgaswitcheroo)

Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201

Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-02-19 19:15:40 +01:00
Paul Menzel 3fee215a3e apple/macbook21: Remove unused include `smbios.h`
Change-Id: I4ed7a164323a71d95a37ea754ec923ca0c5e6219
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18388
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
2017-02-18 23:41:27 +01:00
Denis 'GNUtoo' Carikli 418e808fa6 boardstatus: wiki: Update XiVO's coreboot fork source address
This company doesn't do custom hardware anymore and doesn't
host the sources anymore. We therefore point to the archived
sources instead.

Change-Id: I5ce4f6a468b852fc1d0947fe2b28a5297f14c437
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/11889
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins)
2017-02-18 23:40:51 +01:00
Robbie Zhang e65affa2ed soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.

BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.

Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-18 06:30:53 +01:00
Arthur Heymans ef7e98a2ac nb/intel/x4x: Implement resume from S3 suspend
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.

Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).

Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 23:44:36 +01:00
Arthur Heymans 97e13d84c3 nb/intel/x4x: Fix raminit on reset path
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.

This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
  power supply to remain on, which gets cut off by a cold reset,
  causing data corruption.

To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.

Calling a hot reset after raminit "outb(0x6, 0cf9)" works.

Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18009
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-17 23:44:06 +01:00
Rizwan Qureshi 17335fab17 soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
Add APIs and required parameters for creating Maxim 98927
and Realtek 5336 SSP endpoints in NHLT table.

BUG=chrome-os-partner:62051
BRANCH=None
TEST=check that NHLT table created is created properly

Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: M Naveen <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/18213
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17 19:26:15 +01:00
Rizwan Qureshi 4979d7610e driver/i2c/max98927: add i2c driver for Maxim 98927 codec
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.

BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.

Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: M Naveen <naveen.m@intel.com>
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://review.coreboot.org/18211
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17 19:12:12 +01:00
Rizwan Qureshi ceccb6ba53 mainboard/eve: select SOC_INTEL_KABYLAKE
eve is based on Kabylake SoC hence select the appropriate
config.

Change-Id: I756dda5a1924e83a02ac1cebb1907884f436a13f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18314
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17 19:02:47 +01:00
Rizwan Qureshi b2b98f7ae1 mainboard/poppy: select SOC_INTEL_KABYLAKE
poppy is based on Kabylake SoC hence select the appropriate
config.

Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18313
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17 19:02:30 +01:00
Rizwan Qureshi 0700dca969 soc/intel/skylake: Add config option for Kabylake
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.

Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18312
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-17 19:01:54 +01:00
Paul Menzel 7c7b176169 grub: Build module `boottime`
Configure GRUB to build with boot time statistics. That allows users
to add that module to GRUB by adding `boottime` to the list of extra
modules.

Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-02-17 18:23:23 +01:00
Mathias Krause 898de6111a libpayload: multiboot - support meminfo flag
Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.

Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().

Tested with a multiboot enhanced version of FILO.

Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18350
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-17 18:20:38 +01:00
Robbie Zhang 2b194d9741 intel/skylake: add function is_secondary_thread()
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.

Potentially this function can be put to common code or arch/x86 or cpu/x86.

BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.

Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18366
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 17:46:05 +01:00
Mathias Krause d2f16cac74 libpayload: x86/head - implement argc/argv handling
Implement the argc/argv passing as described in coreboot’s payload API:
http://www.coreboot.org/Payload_API

While at it, give the code some love by not needlessly trashing register
values.

Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-17 17:29:40 +01:00
Mathias Krause 57dc93c967 libpayload: x86/exec - simplify and robustify the code
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.

Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.

Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.

Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-17 17:27:55 +01:00
Mathias Krause 7b681c5926 libpayload: x86/main - propagate return value of main()
According to coreboot’s payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.

[1] https://www.coreboot.org/Payload_API

Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 17:25:11 +01:00
Mathias Krause 9fa78c136d libpayload: x86/exec - fix argc/argv value passing
According to coreboot’s payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.

[1] https://www.coreboot.org/Payload_API

Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 17:24:08 +01:00
Furquan Shaikh c57c48bd36 mainboard/google/poppy: Generate digitizer node in SSDT
Add support for generating digitizer node in SSDT using wacom i2c
driver.

BUG=None
BRANCH=None
TEST=Verified that the node shows up in SSDT.

Change-Id: If7e1e2463778c2ff7263eff995def149457edcde
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18373
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 08:06:54 +01:00
Furquan Shaikh 231c198e2c mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully. Verified that the SSDT entry matches the
entry in mainboard.asl

Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18343
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:42:38 +01:00
Furquan Shaikh 20a91c9830 drivers/spi: Add support for generating SPI device in SSDT
Similar to I2C driver, add support for generating SPI device and
required properties in SSDT for ACPI.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles succesfully. Verified SPI device generated in SSDT on
poppy.

Change-Id: Ic4da79c823131d54d9eb3652b86f6e40fe643ab5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18342
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:42:24 +01:00
Furquan Shaikh 0de80da24c soc/intel/skylake: Add support for SPI device
Add a new PCI driver for SPI devices with supported PCI ids. Also,
provide a translation table to convert struct device structure into SPI
bus number.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Change-Id: If860eb819f2ce5ae5443f808b356af57f86c52be
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18341
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:42:08 +01:00
Furquan Shaikh 4e08479688 device: Add scan_generic_bus support
scan_smbus routine does not perform any smbus specific operation. Thus,
rename the routine to scan_generic_bus so that it can be used by other
buses like SPI. Add a wrapper scan_smbus to allow other users of smbus
scan to continue working as before.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Change-Id: I8ca1a2b7f2906d186ec39e9223ce18b8a1f27196
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18363
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-16 08:41:52 +01:00
Furquan Shaikh 7606c377f5 device: Add a new "SPI" device type
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.

Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.

Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18340
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-16 08:41:28 +01:00
Furquan Shaikh e67002968b sconfig: Add a new "SPI" device type
Update sconfig lex and yacc files to add support for a new "SPI" device
type in the devicetree. SPI device takes only parameter i.e. chip select
number for the device on the SPI bus.

Re-generate the shipped files for sconfig using flex 2.6.0 and bison
3.0.4 (make CONFIG_SCONFIG_GENPARSER=1). Clean up local paths that leak
into generated files.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.

Change-Id: If0831e25b3e4ed87827ad92356d7bf47b6387884
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18339
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:41:15 +01:00
Furquan Shaikh dc1b294bfb soc/intel/skylake: Add GSPI controller get_config support
Provide implementation of get_config routine for GSPI controller on
skylake platforms.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.

Change-Id: I5170076c15d72a7f29acd0989acef5b9149e2ba0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18338
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:41:01 +01:00
Furquan Shaikh 3e01b633d6 spi: Add function callback to get configuration of SPI bus
Add a new callback to spi_ctrlr structure - get_config - to obtain
configuration of SPI bus from the controller driver. Also, move common
config definitions from acpi_device.h to spi-generic.h

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16 08:40:47 +01:00
Sooi, Li Cheng c76e9982b2 soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC
Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC

Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7
Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Reviewed-on: https://review.coreboot.org/18028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-16 05:09:13 +01:00
Mathias Krause 901efea8ab libpayload: x86/exec - fix return value passing
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.

Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18332
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-15 21:56:14 +01:00
Mathias Krause d42c38b93c libpayload: x86/exec - fix libpayload API magic value
According to coreboot’s payload API [1] the magic value passed to the
payload should be 0x12345678, not 12345678. Fix that.

[1] https://www.coreboot.org/Payload_API

Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-15 21:55:21 +01:00