Commit Graph

21397 Commits

Author SHA1 Message Date
Marshall Dawson 9d6b8b4d68 soc/amd/stoneyridge: Fix device IDs
Update pci_devs.h to the correct IDs for Stoney Ridge.

BUG=chrome-os-partner:62578372

Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20200
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28 18:24:15 +00:00
Marshall Dawson 89bb6ab40a amd/family15h: Add defines for boost and P-state
Add definitions for the P-state 0 MSR and Core Performance Boost
Control.

BUG=chrome-os-partner:62578062

Change-Id: I0c16dde17f1be41a3310c3ccefe3936aba0e8ec0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28 18:24:07 +00:00
Marshall Dawson 94ee937e7a soc/amd/stoneyridge: Enable early cbmem
Add a memmap file with a cbmem_top() function.  Remove the
LATE_CBMEM_INIT, allowing the default of EARLY.  Remove calls
to the late-only set_top_of_ram() function.

Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28 18:24:01 +00:00
Marshall Dawson 2185798019 amd/gardenia: Init cbmem in romstage
Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28 18:23:44 +00:00
Martin Roth f5c3518f0e src/ec: add IS_ENABLED() around Kconfig symbol references
Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-28 17:49:22 +00:00
Martin Roth b3b114c28f src/device: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28 17:48:57 +00:00
Martin Roth ebade5dec9 device/oprom/yabel: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28 17:48:49 +00:00
Martin Roth ffdee287df cpu/intel: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28 17:48:42 +00:00
Martin Roth 5f46af6325 cpu/amd: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I9f4155285529ec28e826637a61436478f648704c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28 17:48:34 +00:00
Kevin Cheng 2a6f4aecfe mainboard/google/fizz: Add audio devices
- Describe RT5663 headphone codec in ACPI so it can
be enumerated by the OS.

- Supply NHLT binaries for RT5663

BUG=b:62872377
TEST=Apply full patch set and UCM, verify basic audio works.

Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076
Reviewed-on: https://review.coreboot.org/20305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-28 17:39:51 +00:00
Patrick Rudolph 837da6ade7 libpayload: Add mouse cursor driver
Add a driver to handle multiple low level mouse drivers
and provide basic cursor acceleration support.

Tested on Lenovo T500.

Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:56:53 +00:00
Arthur Heymans 8eb55bbfe7 nb/amdk8/debug.c Fix building with CONFIG_DEBUG_SMBUS
Problem was introduced by fb2f667da2 "nb/amd/amdk8: Link raminit_f.c"
which linked debug.c and was not tested with this option.

Change-Id: I8597a6915c65ea783a864110cb23ecb34ea0611b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:50:08 +00:00
Arthur Heymans 4988af8ca8 util/superiotool: Check for libpci before builing
Check is adapted from inteltool's Makefile.

Change-Id: Ife01ef20d9284cb0a68719757856f9a66a4de452
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:49:32 +00:00
Arthur Heymans 3b633bbf1d cpu/intel/pineview: Include speedstep
Needed to generate cpu entries.

Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:48:41 +00:00
Elyes HAOUAS 27e1801ea7 northbridge/amd/agesa/*: Add whitespace around '<<'
Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:23:39 +00:00
Elyes HAOUAS 168ef399c4 cpu/*: Add whitespace around '<<'
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:23:32 +00:00
Elyes HAOUAS 70083a1de9 payloads: Add whitespace around '<<'
Change-Id: I0659f6ec59fb808b4cedf57d60d737c13c250042
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20396
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:23:18 +00:00
Stefan Reinauer 42b37f537f clang: Allow initializer overrides
In the code we do the following in a number of places
to pre-initialize an array with a certain value before
overwriting some of the array with other values:

 u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
    [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
 }

clang does not like that behavior unless we specify
the option -Wno-initializer-overrides.

Remove the check for gcc in those places, too, because
 1) it would silently change array contents between compilers
 2) the check isn't sufficient to determine compilation on
    clang vs gcc

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc
Reviewed-on: https://review.coreboot.org/20384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 23:54:03 +00:00
Patrick Georgi 0b4d5648f2 xcompile: silence clang when referencing packed structs' members
clang complains that the access might be unaligned. Yes, we know. Yes,
that's exactly what we want. You have _one_ job.

Change-Id: I5400f50d8b5b462270c700f7ff90d9d517278e71
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/19659
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27 23:53:47 +00:00
Stefan Reinauer cb3205d153 sis/sis966: Clean up sata.c
Wow, this one is disliked by clang for the empty for() loop, but
looking at the file just makes my eyes bleed a little bit. I remember
the circumstances under which we let this code go in. It was supposed
to save contributions from a vendor, but that never worked out.
Just to keep the little chunks down, here's an indent run and some of
the cruft removed that doesn't actually contribute to functionality in
any way.

Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 23:50:59 +00:00
Lee Leahy f968a4c970 commonlib/storage: Zero extend MMC capacity
Fix CID 1376472 detected by coverity.  Zero extend the capacity instead
of sign extending it.

TEST=Build and run on reef

Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27 21:55:49 +00:00
Patrick Georgi f138320f9e xcompile: Also try clang variants under the $triplet-clang scheme
That seems to be the more reliable way to build clang cross compilers
for now.

Change-Id: I14fe767d20f91b64e96c909291760bddcd108e5c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/19660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 20:57:34 +00:00
Marshall Dawson c6ef9dbd94 soc/amd/stoneyridge: Add tseg size to Kconfig
Add a SMM_TSEG_SIZE symbol that can be used in top of memory
calculations.

Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27 20:52:13 +00:00
Marshall Dawson 7edba2e134 soc/stoneyridge: Remove IDE controller
Remove IDE from the Stoney Ridge source.  This APU doesn't have
an IDE controller.  The support was left over from pi/hudson.

BUG=chrome-os-partner:62580062

Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 20:52:02 +00:00
Marshall Dawson 6a9f846bcd soc/stoneyridge: Remove FCH PCIe support
Remove the pcie.c file.  Historically PCIe lanes have been
available from the Gfx and/or the FCH.  The integrated FCH in
this APU has no PCIe available.

BUG=chrome-os-partner:62580062

Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 20:51:55 +00:00
Marshall Dawson 8a906dff84 soc/amd/stoneyridge: Remove PCIe-PCI bridge
The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs.  Remove this support from the source.

This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c.

BUG=chrome-os-partner:62580062

Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 20:51:46 +00:00
Marshall Dawson f3dc71e031 soc/amd/common: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the
remaining ones as todo.  Some of the lines requiring a >80
break are indented too much currently.

Changes to agesawrapper.c cause the build to change, so this
file is also left as-is.  Make hex values consistently lower-case.

BUG=chrome-os-partner:622407746

Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 20:51:39 +00:00
Marshall Dawson 4e101ada37 soc/amd/stoneyridge: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the
remaining ones as todo.  (Some of the lines requiring a >80
break are indented too much currently.)  Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.

Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.

These changes were confirmed to cause no changes in a Gardenia
build.  No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().

BUG=chrome-os-partner:622407746

Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 20:50:54 +00:00
Rajneesh Bhardwaj 4692e2fc95 mainboard/google/soraka: Update VR config settings
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline
VR config settings as per board design.

BUG=b:62063434
BRANCH=none
TEST=Build and boot soraka.

Change-Id: I254bbb88b82ddf278f0ec71bc98873df1d5e0d27
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: G Naveen <naveen.g@intel.com>
Reviewed-on: https://review.coreboot.org/20309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27 20:46:48 +00:00
Rajneesh Bhardwaj b3f2c9ac59 mb/google/soraka: Remove MPS IMVP8 workaround
Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.

BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.

Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27 20:46:40 +00:00
Elyes HAOUAS 106e28582c nb/intel/fsp_rangeley/port_access.c: Add brackets around macro
Code checked manually

Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 19:44:04 +00:00
Elyes HAOUAS 7c4a8e57dc libpayload/drivers/usb/ehci_private.h: Add brackets around macro
Change-Id: Iee8dc03d5a4ca7537c7da4fed2c67b169c9e2422
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27 19:43:22 +00:00
Elyes HAOUAS 47916fbef2 libpayload/drivers/usb/xhci_private.h: Add parentheses around macro
Change-Id: I0347594e9480dedc4845b6863733a67fc5e47e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20371
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27 19:43:15 +00:00
Martin Roth 037dbe42d7 util/lint: Add check to make sure 'coreboot' is lowercase
- Excludes certain phrases which can't be changed.
- Checks last commit message if code is in a repo.

Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20032
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27 18:59:24 +00:00
Marshall Dawson 6744dfe7e0 soc/amd/stoneyridge/acpi: Fix checkpatch errors
Correct the checkpatch errors reported in the asl files and
make other stylistic modifications.

These changes were confirmed to cause no changes in a Gardenia
build.

BUG=chrome-os-partner:622407746

Change-Id: Id8b2620d161062c444e493325d83bb158705b76b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27 18:36:29 +00:00
Martin Roth a564811e71 util: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Change-Id: I0a024d82d331c0794fe087e440b4e1924129a13c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 18:26:01 +00:00
Nico Huber cd87e1ba2d buildgcc: Adapt messages about GNAT and bootstrapping
Don't ask for bootstrapping in case of a different host GCC major
version. GCC's versioning scheme changed starting with the release
of GCC 5. There are no big changes between the versions any more.
Instead, show the message when the host GCC's version is below 4.

In case GNAT can't be found, ask the user to abort and install it.
Also give hints for Ubuntu where the package versions are a little
messy (e.g. the meta packages gcc and gnat often point to different
versions).

In case GNAT is found but is too old (< 4.9), enable bootstrapping
by default and tell the user that building will take longer.

In all three cases show a timeout to draw the user's attention.

v2: Update GNAT check to also look for `gnatbind`. It has to be
    somewhere in $PATH.

Change-Id: I4d9de11d7469e137ede8ad138296d20c0f8ba78f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20332
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 18:24:29 +00:00
Nico Huber 18c74d69af buildgcc: Rename quit() to exit_handler()
"quit" is a signal name. The FreeBSD `sh` interprets

    trap quit 1 2 3 15

as command to reset all the respective signal handlers, instead
of setting quit() as handler.

Change-Id: I69b813ab583f15a9dd89a115f7aea66d966f981b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20391
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27 18:24:10 +00:00
Stefan Reinauer 8d29dd1258 vendorcode/amd: Unify Porting.h across all targets
This requires to also unify the calling convention for
AGESA functions from
 AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
 AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)

On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.

Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27 17:35:39 +00:00
Patrick Rudolph a26dbbd9d0 soc/intel/common/opregion: Use enum cb_err as return value
Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.

Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 17:18:03 +00:00
Martin Roth 33232604a7 nb/intel: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-27 17:16:19 +00:00
Nicola Corna 71693ba43f coreinfo: Use regular `if` over `#if` for `IS_ENABLED`
When using the regular `if` construct, the compiler will check
the guarded code independently from the condition.

Change-Id: I00c5c7ae3720f75aa9415edb94cd2ce76cee8aee
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27 17:16:03 +00:00
Stefan Reinauer 5f98f98098 soc/intel/quark: We're not Broadwell anymore
... even though the author of the code probably wished he was
working on a (much faster) broadwell system instead. Let's fix
the header guard to reflect the right SOC.

Noteworthy: clang detected that this was wrong.

Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:09:23 +00:00
Stefan Reinauer bc3150913b northbridge/amd/pi: Arithmetics is not logic
It's pretty obvious that the author did not want to use a logical
and (&&) here but an arithmetical and (&)

Change-Id: Ic1bece86986906b76308bbb46235c22418e27990
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:04:55 +00:00
Stefan Reinauer 5128f1b593 README: Update requirements
pkg-conf and libssl-dev are needed for abuild to run successfully on
all boards.

Change-Id: Ic0ca2036751893ac4bd3ff17c53fe518b22b64ad
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:04:32 +00:00
Stefan Reinauer 67ed261200 amd/amdfam10: Remove dead code
dual_node is never used in that function. And it is never set
correctly either, because the register f3xe8 is never actually
read either. Just remove the whole useless construct.

Change-Id: If316da89bceae6b162f20e4b632276db2d9ef423
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:02:49 +00:00
Stefan Reinauer e06e2fdce1 drivers/spi: Don't disable non-existent warnings on clang
The warning -Wstack-usage= doesn't seem to exist on clang, so trying
to disable it makes the compiler unhappy about non-existent pragmas.
Catching this on gcc is good enough, so let's disable it for the clang
case

Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:00:55 +00:00
Stefan Reinauer 8e6bb80e9a vendorcode/amd: Satisfy clang's bracing requirements
src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error:
suggest braces around initialization of subobject

Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:00:27 +00:00
Stefan Reinauer c02b5e22a3 vendorcode/amd: Make compiler intrinsics clang friendly
Change-Id: Ibff31a9960a23f03facbb09e76d6a5d6fbfb5e94
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27 17:00:14 +00:00
Elyes HAOUAS b09822cf82 libpayload/drivers/usb/ohci_private.h: Add brackets around macro
Change-Id: Id4892adba161cd08eecde71a011384b6c465b98f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27 16:51:30 +00:00